Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Abstract: Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

Abstract: Hybrid memory architecture technologies are described. In accordance with embodiments disclosed herein, there is provided a processing device having a core and a memory controller communicably coupled to the core to receive a request to fetch data. The memory controller is communicably coupled to a hybrid memory architecture including a near memory, wherein the near memory is divided into a flat memory region and a cache memory region.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

Abstract: A method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images are provided. The method of rendering high resolution images based on sub-band encoded data of an image includes steps of performing downscaling of a selected image, creating a time-stamped downscaled image, extracting sub-band information associated with the selected image at one instance in time, compressing the downscaled image and the sub-band information, and decompressing and adding the sub-band information with extrapolated downscaled image to reconstruct and render high resolution image.

Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Abstract: Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

Abstract: Techniques for the discovery of a topology of varying complexity and discovery of the capability of the devices of the topology include querying a plurality of node devices for node data. At least an initial portion of node data of one or more node devices is received in response to the query. In addition, previously determined node data is retrieved from a cache. The initial portion of node data is correlated to the previously determined node data to deduce node data for one or more node devices within a predetermined period of time. It is to be appreciated that the deduced node data may include node data beyond the initial portion of node data and/or node data for other node devices beyond the initially responding node devices. The deduced node data may then be reported to an operating system.

Abstract: Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits. In embodiments, one or more error detection modules may be configured to detect a plurality of error types in the codeword. One or more error correction modules coupled with the one or more error detection modules may be further configured to correct errors of the plurality of error types once they are detected by the one or more error detection modules. Other embodiments may be described and/or claimed.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.

Abstract: A system and method are provided for displaying a video signal concurrently on a plurality of display devices. The system includes an operating system (OS) and a device driver. The device driver identifies a subset of display devices connected to the system, where the subset includes two or more of the display devices. The device driver also connects to the OS a virtual display device that is representative of the subset of display devices. The device driver further configures the system to route a video signal to all of the subset of display devices.

Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Abstract: In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.