Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

Abstract: Techniques for the discovery of a topology of varying complexity and discovery of the capability of the devices of the topology include querying a plurality of node devices for node data. At least an initial portion of node data of one or more node devices is received in response to the query. In addition, previously determined node data is retrieved from a cache. The initial portion of node data is correlated to the previously determined node data to deduce node data for one or more node devices within a predetermined period of time. It is to be appreciated that the deduced node data may include node data beyond the initial portion of node data and/or node data for other node devices beyond the initially responding node devices. The deduced node data may then be reported to an operating system.

Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.

Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.

Abstract: In some embodiments, a chip includes a scheduler, transmitters, receivers, and control circuitry. The schedule schedules signals to be transmitted outside the chip and the transmitters transmit the scheduled signals outside the chip. The receivers receive signals including signals with temperature information related to a temperature outside the chip. The control circuitry selectively limit a number of commands that can be scheduled within a series of smaller windows while checking the temperature information near the conclusion of a larger window comprising many smaller windows. Other embodiments are described.

Abstract: In some embodiments, a chip includes chip interface transmitters, a chip, and clock gearing logic. The transmitters are to transmit signals in frames including slots. The scheduler is to schedule signals at a first frequency including commands for first slots of the frames in general and commands for second slots of at least some frames immediately preceding frequency mismatch bubbles occurring when the frames are at a second frequency. The clock gearing logic is to provide the signals having the first frequency from the scheduler to the transmitters at the second frequency. Other embodiments are described.

Abstract: Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.

Abstract: The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Abstract: Methods and apparatuses for including synchronization data to be used for parallel processing in a block of data having error correcting code symbols. The block of data is encoded using an error correcting code. The resulting encoding includes three check symbols per 32 data symbols. At least one synchronization symbol corresponding to the data symbols is generated. The data symbols, the check symbols and the at least one synchronization symbol are combined. The combined data symbols, the check symbols and the at least one synchronization symbol are transmitted.

Abstract: A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue.

Abstract: This invention relates to compositions useful as adhesives and more particularly to the preparation of heat-cured epoxy-based adhesive compositions with improved impact resistance and good adhesion to oily metal substrates.

Abstract: This invention relates to compositions useful as adhesives and more particularly to the preparation of heat-curable epoxy-based adhesive compositions that are capable of being easily pumped under high shear at temperatures around room temperature but are resistant to being washed off substrate surfaces prior to being cured.

Abstract: In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.

Abstract: Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The N-bit CRC is used if at least one bit-lane of the memory channel fails. In one embodiment, the memory controller selectively applies the strong error detection capability of an error correction code (ECC) in combination with the N-bit CRC to signal the need to resend faulty data, if at least one bit-channel has failed. Other embodiments are described and claimed.

Abstract: According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for mitigating silent data corruption using an error correction code having embedded signaling fault detection. In an embodiment, a memory controller includes an extended error correction code (ECC) and link signaling fault detection logic. The extended ECC includes embedded signaling fault detection. In one embodiment, the extended ECC augments the signaling fault detection capabilities of the signaling fault detection logic.

Abstract: Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.

Abstract: The present disclosure provides a method for reducing memory traffic in a distributed memory system. The method may include storing a presence vector in a directory of a memory slice, said presence vector indicating whether a line in local memory has been cached. The method may further include protecting said memory slice from cache coherency violations via a home agent configured to transmit and receive data from said memory slice, said home agent configured to store a copy of said presence vector. The method may also include receiving a request for a block of data from at least one processing node at said home agent and comparing said presence vector with said copy of said presence vector stored in said home agent. The method may additionally include eliminating a write update operation between said home agent and said directory if said presence vector and said copy are equivalent. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.