Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.

Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.

Abstract: A multiplying digital to analog converter (MDAC) includes a first resistor configured to be selectively connected to a current output node based on a first bit of a first portion of an input digital code and a second resistor configured to be selectively connected to the current output node based on a second bit of the first portion of the input digital code. A resistance of the second resistor is a resistance of the first resistor scaled by a factor. The MDAC further includes a first capacitor configured to be selectively connected to the current output node based on the first bit of the first portion and a second capacitor configured to be selectively connected to the current output node based on the second bit of the first portion. A capacitance of the second capacitor is a capacitance of the first capacitor scaled by an inverse of the factor.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: At least some embodiments are directed to a system comprising a capacitor coupled to a voltage supply rail and configured to carry a capacitor current that comprises first and second parts. The capacitor current is an alternating current (AC). A first current mirror component may couple to the capacitor and to the voltage supply rail and is configured to carry the first part of the capacitor current. A second current mirror component couples to the voltage supply rail and is configured to carry the second part of the capacitor current. The second part of the capacitor current is proportionally related to the first part of the capacitor current. A circuit couples to the second current mirror component. The capacitor and the first and second current mirror components are configured to attenuate a common mode noise current flowing to the circuit.

Abstract: Disclosed examples include switched capacitor integrator circuits including an amplifier, a feedback capacitor, a sampling capacitor, a loading capacitor and a switching circuit, along with a controller that operates the switching circuit to sample an input signal to the sampling capacitor during a sample portion of a given sample and hold cycle, to couple the sampling capacitor to an amplifier input during a first hold portion of each sample and hold cycle, and to couple the sampling capacitor and the loading capacitor to the amplifier input in a second hold portion of each sample and hold cycle to reduce the bandwidth and power consumption by the integrator circuit.

Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.

Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.

Abstract: A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.

Abstract: A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.