Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A sampled CMOS switch includes first and second NMOS devices in series between input and output nodes. The first and second NMOS devices are activated by a sample signal. A pair of low-voltage DEPMOS devices is connected in a “T” configuration between the input and output nodes. The low-voltage DEPMOS devices are activated by an inverted sample signal. A feedback circuit includes the DEPMOS devices together with a third high-voltage NMOS device and a current source. The third NMOS device is controlled by a signal on the input node. A switch switchably connects an analog voltage source to a source of the third NMOS device and gates of the DEPMOS devices in accordance with a phase of an inverted sample signal. The construction of the sampled CMOS switch enables the protection of the gate oxide insulation of the low-voltage DEPMOS transistors from high voltage damage.

Abstract: A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

Abstract: A dynamic biasing circuit includes a first input pair coupled to a second input pair, the first input pair including a first transistor and a second transistor with sources coupled to each other, and the second input pair comprising a third transistor and a fourth transistor with sources coupled to each other, the sources receiving a bias current. A first current mirror that generates an output current is coupled to the first input pair. A second current mirror is coupled to the first input pair and the second input pair. The second current mirror is configured to force the current to drop in the fourth transistor in response to sensing a current drop in the first transistor such that the bias current flows through the second and third transistors that boosts the output current.

Abstract: A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.

Abstract: A voltage-mode driver circuit supporting pre-emphasis includes multiple resistors, and multiple transistors operated as switches. Control signals operating the transistors represent a logic level of an input signal to the driver circuit. To generate a pre-emphasized output, the transistors are operated to connect a parallel arrangement of the resistors between output terminals of the driver and corresponding constant reference potentials. To generate an output in the steady-state, the transistors are operated to connect some of the resistors across the output terminals of the driver, thereby reducing the output voltage. A desired output impedance of the driver, and a desired level of pre-emphasis are obtained by appropriate selection of the resistance values of the resistors. The current consumption of the driver is less in the steady-state than in the pre-emphasis mode.

Abstract: A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.