Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Abstract: A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing write requests in an order based on information in the read queue. When the write queue is under the low watermark, the method includes stopping the draining of the write queue and again processing the read requests in the read queue.

Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

Abstract: Techniques for memory device writes based on mapping are provided. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise multiple memory devices. The block of data may be written to a number of memory devices determined by the size of the block of data. A memory device mapping for the line may be retrieved. The mapping may determine the order in which the block of data is written to the memory devices within the rank. The block of data may be written to the memory devices based on the mapping.

Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.

Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.

Abstract: An example system in accordance with an aspect of the present disclosure is to use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED is to be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC information, in response to identifying the error.

Abstract: The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Abstract: A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition the example apparatus includes a column decoder (606) to selectively activate a portion of the raw based on the column address and the signal asserted on the wordline.

Abstract: An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Abstract: A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error.

Abstract: A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.

Abstract: The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

Abstract: A method for managing memory includes storing a history of accesses to a memory page, and determining whether to keep the memory page open or to close the memory page based on the stored history. A memory system includes a plurality of memory cells arranged in rows and columns, a row buffer, and a memory controller configured to manage the row buffer at a per-page level using a history-based predictor. A non-transitory computer readable medium is also provided containing instructions therein, wherein the instructions include storing an access history of a memory page in a lookup table, and determining an optimal closing policy for the memory page based on the stored histories. The histories can include access numbers or access durations.

Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.