Patents by Inventor Rajeev Balasubramonian

Rajeev Balasubramonian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiple clock domain microprocessor
    Patent number: 7739537
    Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: June 15, 2010
    Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
  • DYNAMICALLY MANAGING THE COMMUNICATION-PARALLELISM TRADE-OFF IN CLUSTERED PROCESSORS
    Publication number: 20090216997
    Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.
    Type: Application
    Filed: January 12, 2009
    Publication date: August 27, 2009
    Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
  • Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals
    Patent number: 7490220
    Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: February 10, 2009
    Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
  • Microarchitectural wire management for performance and power in partitioned architectures
    Patent number: 7478190
    Abstract: A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: January 13, 2009
    Assignee: University of Utah Technology Commercialization Office
    Inventors: Rajeev Balasubramonian, Liqun Cheng, John Carter, Naveen Muralimanohar, Karthik Ramani
  • Microarchitectural wire management for performance and power in partitioned architectures
    Publication number: 20070192541
    Abstract: A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically routing traffic in a processor environment.
    Type: Application
    Filed: February 10, 2006
    Publication date: August 16, 2007
    Inventors: Rajeev Balasubramonian, Liqun Cheng, John Carter, Naveen Muralimanohar, Karthik Ramani
  • Multiple clock domain microprocessor
    Publication number: 20070016817
    Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
    Type: Application
    Filed: March 27, 2006
    Publication date: January 18, 2007
    Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
  • Multiple clock domain microprocessor
    Patent number: 7089443
    Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: August 8, 2006
    Assignee: University of Rochester
    Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael L. Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
  • Dynamically managing the communication-parallelism trade-off in clustered processors
    Publication number: 20060106923
    Abstract: In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.
    Type: Application
    Filed: June 8, 2005
    Publication date: May 18, 2006
    Inventors: Rajeev Balasubramonian, Sandhya Dwarkadas, David Albonesi
  • Multiple clock domain microprocessor
    Publication number: 20050060597
    Abstract: A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately generated clock, and synchronizing circuits ensure reliable inter-domain communication. Thus, fully synchronous design practices are used in the design of each domain.
    Type: Application
    Filed: January 23, 2004
    Publication date: March 17, 2005
    Inventors: David Albonesi, Greg Semeraro, Grigorios Magklis, Michael Scott, Rajeev Balasubramonian, Sandhya Dwarkadas
  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
    Patent number: 6834328
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: December 21, 2004
    Assignee: University of Rochester
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
    Publication number: 20040184340
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Application
    Filed: January 27, 2004
    Publication date: September 23, 2004
    Applicant: UNIVERSITY OF ROCHESTER
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Dynamic reconfigurable memory hierarchy
    Patent number: 6684298
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: January 27, 2004
    Assignee: University of Rochester
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosnoglu, David Albonesi
  • Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
    Patent number: RE41958
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 23, 2010
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu, David H. Albonesi
  • Dynamic reconfigurable memory hierarchy
    Patent number: RE42213
    Abstract: A cache and TLB layout and design leverage repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: March 8, 2011
    Assignee: University of Rochester
    Inventors: Sandhya Dwarkadas, Rajeev Balasubramonian, Alper Buyuktosunoglu, David H. Albonesi