Abstract: An object storage data store may be implemented using storage devices providing multiple extents, where individual ones of the extents include multiple independently addressable, contiguous blocks and where updating an extent is performed by updating the respective independently addressable, contiguous blocks sequentially using a series of write operations. The storage devices may include shingled magnetic recording devices and may include conventional persistent storage devices. The key value data store may implement a superblock structure, index structure, and data store structure using respective portions of the multiple extents, where updates to each of the structures is performed sequentially using a series of write operations. The key value data store may further implement a cache for the index structure to minimize input-output (IO) density of the object storage data store.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Embodiments of the present invention relate to a method of forming a magnetics package. The method includes providing a primary coil configured to conduct a current flow; providing a substrate having a surface and a secondary coil extending from the surface, the secondary coil configured to conduct a current flow; encapsulating the secondary coil in a secondary mold compound; removing the substrate from the secondary coil, thereby leaving the secondary coil embedded in the secondary mold compound; and inductively coupling the secondary coil to the primary coil through a magnetic core, the secondary coil is electrically isolated from the primary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A leadframe based photovoltaic assembly and method for assembling the same is disclosed. The photovoltaic assembly comprises a first and second mold compounds to effectuate the accurate placement of an optical concentrator above a photovoltaic cell. The photovoltaic assembly is able to be assembled using existing mature semiconductor packaging technologies.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract: One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.

Abstract: Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices.

Abstract: A magnetics package comprising: a primary coil configured to conduct a current flow; a secondary coil electrically isolated from the primary coil and configured to conduct a current flow, wherein the secondary coil is embedded in a mold compound; and a magnetic core inductively coupling the primary coil and the secondary coil, wherein a current flow in the primary coil produces a magnetic field in the magnetic core, and the magnetic field in the magnetic core induces a current flow in the secondary coil.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Abstract: A shielding assembly is configured to provide electromagnetic shielding and environmental protection to one or more electronic components coupled to a substrate. The shielding assembly includes a non-conductive mold compound layer, such as a dielectric epoxy. The mold compound layer is applied to a top surface of the substrate, thereby covering the electronic components and providing protection against environmentally induced conditions such as corrosion, humidity, and mechanical stress. The shielding assembly also includes a conductive layer applied to a top surface of the mold compound layer. The conductive layer is coupled to a ground plane in the substrate, thereby enabling the electromagnetic shielding function. The conductive layer is coupled to the ground plane via one or more metallized contacts that are coupled to the substrate and extend through the mold compound layer.

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.