Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract: A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: A chip device including two stacked dies. The chip device includes a leadframe that includes a plurality of leads. A first die is coupled to a first side of the leadframe with solder and a second die is coupled to a second side of the leadframe with solder. A molded body surrounds at least a portion of the leadframe and the dies.

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: An integrated transistor module includes a lead frame that defines at least one low-side land and at least one high-side land. A stepped portion of the lead frame mechanically and electrically interconnects the low-side and high-side lands. A low-side transistor is mounted upon the low-side land with its drain electrically connected to the low-side land. A high-side transistor is mounted upon the high-side land with its source electrically connected to the high-side land.

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract: An integrated circuit assembly includes a lead frame having a plurality of leads with inner portions. A thermally-conductive clip member is bonded to the inner portions of the leads such that the clip member is electrically isolated from and yet thermally coupled to the lead frame. An integrated circuit die is bonded and thereby thermally coupled to the clip member. The die is electrically connected to the wire die by wire bonds. Encapsulant material is disposed over the inner portions of the leads and at least a portion of the clip member, and encapsulates the die and the wire bonds.

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the die serves as a drain connection while the solder balls serve as the source and gate connections.