Patents by Inventor Rajeev Kumar Dokania
Rajeev Kumar Dokania has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250225095Abstract: Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.Type: ApplicationFiled: March 4, 2025Publication date: July 10, 2025Applicant: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rajeev Kumar Dokania, Ananda Samajdar, Sasikanth Manipatruni
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Patent number: 12347476Abstract: Described herein is a memory sensing scheme that improves noise margin. In at least one embodiment, one or more circuitries are described that are coupled to a bit-cell, wherein the bit-cell is coupled to a plate-line and a bit-line, wherein the one or more circuitries are to sense a bit-value stored in the bit-cell based, at least in part, on a first floating charge on a plate-line and a second floating charge on a bit-line.Type: GrantFiled: December 27, 2022Date of Patent: July 1, 2025Assignee: Kepler Computing Inc.Inventors: Ahmad Tavakoli, Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Publication number: 20250201778Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.Type: ApplicationFiled: March 3, 2025Publication date: June 19, 2025Applicant: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
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Patent number: 12336184Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.Type: GrantFiled: March 18, 2022Date of Patent: June 17, 2025Assignee: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
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Patent number: 12324162Abstract: A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.Type: GrantFiled: June 17, 2022Date of Patent: June 3, 2025Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Somilkumar J. Rathi, Sasikanth Manipatruni
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Patent number: 12322743Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: June 3, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
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Patent number: 12324163Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.Type: GrantFiled: March 15, 2022Date of Patent: June 3, 2025Assignee: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
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Publication number: 20250169078Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.Type: ApplicationFiled: January 6, 2025Publication date: May 22, 2025Applicant: Kepler Computing Inc.Inventors: Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 12294370Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: September 3, 2021Date of Patent: May 6, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
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Patent number: 12289894Abstract: A method of fabricating a system includes fabricating a plurality of transistors and coupling a forming a bridge structure connected between a gate contact of a first transistor with a drain contact of a second transistor. The method further includes fabricating a multi-level memory structure including capacitors that comprise a ferroelectric material or a paraelectric material. The capacitors within a given level are coupled together by a plate electrode. The method further includes forming a signal electrode coupled with the plate electrode.Type: GrantFiled: June 17, 2022Date of Patent: April 29, 2025Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Somilkumar J. Rathi, Sasikanth Manipatruni, Tanay Gosavi
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Patent number: 12289104Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: September 3, 2021Date of Patent: April 29, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
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Patent number: 12283571Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.Type: GrantFiled: April 14, 2021Date of Patent: April 22, 2025Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya, Debo Olaosebikan
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Patent number: 12283955Abstract: A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: September 10, 2021Date of Patent: April 22, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
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Patent number: 12272675Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.Type: GrantFiled: July 25, 2023Date of Patent: April 8, 2025Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
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Patent number: 12274071Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.Type: GrantFiled: May 31, 2023Date of Patent: April 8, 2025Assignee: Kepler Computing Inc.Inventors: Mauricio Manfrini, Noriyuki Sato, James David Clarkson, Abel Fernandez, Somilkumar J. Rathi, Niloy Mukherjee, Tanay Gosavi, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 12265494Abstract: Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.Type: GrantFiled: August 16, 2023Date of Patent: April 1, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rajeev Kumar Dokania, Ananda Samajdar, Sasikanth Manipatruni
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Patent number: 12262541Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.Type: GrantFiled: March 18, 2022Date of Patent: March 25, 2025Assignee: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
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Patent number: 12243797Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.Type: GrantFiled: September 17, 2021Date of Patent: March 4, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
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Patent number: 12238935Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.Type: GrantFiled: July 27, 2023Date of Patent: February 25, 2025Assignee: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
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Patent number: 12223992Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).Type: GrantFiled: April 28, 2021Date of Patent: February 11, 2025Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh