Patents by Inventor Rajeev Kumar Dokania

Rajeev Kumar Dokania has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11791233
    Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 17, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Amrita Mathuriya, Christopher B. Wilkerson, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
  • Patent number: 11785782
    Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: October 10, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11784164
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 10, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Sasikanth Manipatruni, Amrita Mathuriya, Debo Olaosebikan
  • Patent number: 11777504
    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: October 3, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
  • Publication number: 20230308102
    Abstract: An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 28, 2023
    Applicant: Kepler Computing, Inc.
    Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Guarav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11769790
    Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: September 26, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, Fnu Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
  • Patent number: 11769543
    Abstract: A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: September 26, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11770936
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 26, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Publication number: 20230298905
    Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
    Type: Application
    Filed: February 1, 2022
    Publication date: September 21, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Niloy Mukherjee, Somilkumar J. Rathi, Jason Y. Wu, Pratyush Pandey, Zeying Ren, FNU Atiquzzaman, Gabriel Antonio Paulius Velarde, Noriyuki Sato, Mauricio Manfrini, Tanay Gosavi, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh, Sasikanth Manipatruni
  • Publication number: 20230301113
    Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
  • Patent number: 11764790
    Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: September 19, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh, Sasikanth Manipatruni
  • Patent number: 11765908
    Abstract: A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: September 19, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Mauricio Manfrini, Noriyuki Sato, James David Clarkson, Abel Fernandez, Somilkumar J. Rathi, Niloy Mukherjee, Tanay Gosavi, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11765909
    Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 19, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11764190
    Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 19, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
  • Patent number: 11758708
    Abstract: To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: September 12, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Noriyuki Sato, Tanay Gosavi, Amrita Mathuriya, Sasikanth Manipatruni
  • Patent number: 11757452
    Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 12, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 11758738
    Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: September 12, 2023
    Assignee: KEPLER COMPUTING INC.
    Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Gaurav Thareja, Amrita Mathuriya
  • Publication number: 20230284456
    Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.
    Type: Application
    Filed: March 15, 2022
    Publication date: September 7, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Rajeev Kumar Dokania, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
  • Publication number: 20230284455
    Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.
    Type: Application
    Filed: August 30, 2022
    Publication date: September 7, 2023
    Applicant: Kepler Computing Inc.
    Inventors: Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11748537
    Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: September 5, 2023
    Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya