Patents by Inventor Rajen Murugan

Rajen Murugan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7251302
    Abstract: An apparatus, method and system are provided for quantifying communication channel intersymbol interference jitter effect contribution to timing skew. In general, lossy and lossless characteristics of the communication channel are preferably obtained and an output signal of the communication channel is sampled. From the sampled output signal and the lossy characteristics of the communication channel, an input signal may be derived. Using the lossless characteristics of the communication channel, the derived input signal and the sampled output signal, a value indicating the contribution of intersymbol interference jitter effect on timing skew budget for a selection communication channel may be obtained.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: July 31, 2007
    Assignee: Dell Products L.P.
    Inventors: Rajen Murugan, Michael Greim
  • Publication number: 20060215792
    Abstract: A digital signal waveform receiving circuit may be processed by a non-linear adaptive canonical correlation analysis circuit that may quantify and minimize crosstalk-induced jitter timing skew for improving set-up and hold timing margins of data streams on the receiving circuit. A non-linear adaptive canonical correlation analysis circuit may be placed between an incoming digital signal from a serial link and a PHY receiving layer of an information handling system 100. The PHY receiving layer of the information handling system may be coupled to the non-linear adaptive canonical correlation analysis circuit or may be coupled to the digital signal. This coupling selection may be automatically programmed depending on received signal cross-talk-induced jitter timing skew or may be programmed by a user of the information handling system.
    Type: Application
    Filed: March 24, 2005
    Publication date: September 28, 2006
    Inventors: Rajen Murugan, Girish Singh
  • Publication number: 20060215794
    Abstract: A wavelet transform noise minimization circuit comprises a differential receiver, a voltage comparator, a wavelet transform circuit, an electrical idle (EI) detector circuit, a phase interpolator, a phase-locked-loop (PLL), and a reference clock buffer. The wavelet transform noise minimization circuit may be beneficially applied wherever there is non-deterministic (e.g., random) noise in the PHY layer during an electrical idle state. The wavelet transform noise minimization circuit may be used to improve noise margin during an electrical idle state, and/or reduce the occurrence of false activation of a PHY layer when in the electrical idle state.
    Type: Application
    Filed: March 24, 2005
    Publication date: September 28, 2006
    Inventors: Rajen Murugan, Bhavesh Patel
  • Publication number: 20050231927
    Abstract: A system, apparatus and method for controlled impedance at transitional via sites using barrel inductance minimization are provided. In one embodiment, one or more sidewalls of a via barrel are preferably processed such that conductive material disposed thereon is selectively removed thereby forming an inner-via trace connecting one or more conductive traces and/or pads on a first substrate layer to one or more conductive traces and/or pads on a second substrate layer. Removal of conductive material from a sidewall of the via barrel is done in a manner such that an inner-via trace traveling from a first surface to a second surface of one or more substrate layers possesses at least one electrical characteristic substantially approximating a corresponding electrical characteristic of those structures to which the inner-via trace is connected.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 20, 2005
    Applicant: Dell Products L.P.
    Inventors: Jinsaku Masuyama, Rajen Murugan
  • Publication number: 20050125175
    Abstract: An apparatus, method and system are provided for quantifying communication channel intersymbol interference jitter effect contribution to timing skew. In general, lossy and lossless characteristics of the communication channel are preferably obtained and an output signal of the communication channel is sampled. From the sampled output signal and the lossy characteristics of the communication channel, an input signal may be derived. Using the lossless characteristics of the communication channel, the derived input signal and the sampled output signal, a value indicating the contribution of intersymbol interference jitter effect on timing skew budget for a selection communication channel may be obtained.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 9, 2005
    Applicant: Dell Products L.P.
    Inventors: Rajen Murugan, Michael Greim