Patents by Inventor Rajendra C. Dias

Rajendra C. Dias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11854945
    Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 26, 2023
    Assignee: Tahoe Research, Ltd.
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund
  • Patent number: 10763220
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Mitul B. Modi
  • Patent number: 10685949
    Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Mauro Kobrinsky, Johanna Swan, Rajendra C. Dias
  • Patent number: 10634594
    Abstract: A membrane test for mechanical testing of wearable devices is described. A mechanical testing system includes an actuation mechanism including a clamp to hold a membrane including stretchable electronics over an opening in the actuation mechanism, wherein the actuation mechanism is to apply pressure to the membrane through the opening; and a testing logic to control the application and release of pressure on the membrane by the actuation mechanism.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Ravindranth V. Mahajan, Rajendra C. Dias, Pramod Malatkar, Steven A. Klein, Vijay Subramania, Aleksandar Aleksov, Robert L. Sankman
  • Patent number: 10615128
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Patent number: 10535615
    Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Srikant Nekkanty, Rajendra C. Dias, Patrick Nardi
  • Patent number: 10468357
    Abstract: Embodiments of the invention include a microelectronic device and methods for forming a microelectronic device. In an embodiment, the microelectronic device includes a semiconductor die that has one or more die contacts that are each electrically coupled to a contact pad by a conductive trace. The semiconductor die may have a first elastic modulus. The microelectronic device may also include an encapsulation layer over the semiconductor die and the conductive trace. The encapsulation layer may have a second elastic modulus that is less than the first elastic modulus. The microelectronic device may also include a first strain redistribution layer within the encapsulation layer. The first strain redistribution layer may have a footprint that covers the semiconductor die and a portion of the conductive traces. The strain redistribution layer may have a third elastic modulus that is less than the first elastic modulus and greater than the second elastic modulus.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Tatyana N. Andryushchenko, Mauro J. Kobrinsky, Aleksandar Aleksov, David W. Staines
  • Patent number: 10461007
    Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Nachiket R. Raravikar
  • Publication number: 20190157215
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Inventors: Rajendra C. Dias, Mitul B. Modi
  • Publication number: 20190148268
    Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Inventors: Omkar G. KARHADE, Nitin A. DESHPANDE, Rajendra C. DIAS, Edvin CETEGEN, Lars D. SKOGLUND
  • Patent number: 10229887
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Mitul B. Modi
  • Patent number: 10206277
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Manish Dubey, Tatyana N. Andryushchenko, Aleksandar Aleksov, David W. Staines
  • Patent number: 10192810
    Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Rajendra C. Dias, Edvin Cetegen, Lars D. Skoglund
  • Publication number: 20180323128
    Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic components or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The top portion of the EMI shielding may be a laminated metal sheet provided on a top surface of the molding. The semiconductor package may further have vertical portions of the EMI shielding with conductive ink filled trenches in the molding that may separate one or more electronic components from other electronic components of the semiconductor package.
    Type: Application
    Filed: December 22, 2015
    Publication date: November 8, 2018
    Applicant: INTEL CORPORATION
    Inventors: Rajendra C. Dias, Nachiket R. Raravikar
  • Publication number: 20180226358
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Application
    Filed: April 4, 2018
    Publication date: August 9, 2018
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Patent number: 9991211
    Abstract: Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing metal particles, e.g., conductive particles or magnetic particles, in a resin matrix to attenuate electromagnetic interference. In an example, the shielding layer is transferred from a molding chase to the semiconductor package during a polymer molding operation.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Anna M. Prakash, Reynaldo Alberto Olmedo, Venmathy McMahan, Rajendra C. Dias, Joshua David Heppner, Ann Jinyan Xu, Sriya Sanyal, Eric Jin Li
  • Patent number: 9953929
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate including electrical connection circuitry therein, grounding circuitry on, or at least partially in the substrate, the grounding circuitry at least partially exposed from a surface of the substrate, a die electrically connected to the connection circuitry and the grounding circuitry, the die on the substrate, and a conductive foil or conductive film surrounding the die, the conductive foil or conductive film electrically connected to the grounding circuitry.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Anna M. Prakash, Joshua D. Heppner, Eric J. Li, Nachiket R. Raravikar
  • Publication number: 20180089984
    Abstract: Techniques and mechanisms for determining a level of degradation of flexible circuitry. In an embodiment, a flexible substrate has disposed therein first circuitry and one or more components coupled thereto, the one or more components to monitor a physical property of the first circuitry. Further disposed in or on the flexible substrate are memory resources to store predefined reference information which corresponds amounts of the physical property each with a different respective level of degradation. Evaluation logic accesses the reference information to determine, based on a detected amount of the physical property, a level of degradation of second circuitry. In another embodiment, the second circuitry is more flexible, as compared to the first circuitry.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Vijay Krishnan Subramanian, Steven A. Klein, Pramod Malatkar, Rajendra C. Dias, Aleksandar Aleksov, Jason P. Glumbik, Nadine L. Dabby
  • Patent number: 9887104
    Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Rajendra C. Dias, Patrick Nardi, David Woodhams
  • Publication number: 20180033741
    Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.
    Type: Application
    Filed: February 12, 2016
    Publication date: February 1, 2018
    Inventors: Manish Dubey, Srikant Nekkanty, Rajendra C. Dias, Patrick Nardi