Abstract: A programmable characterization-debug-test engine (PCDTE) on an integrated circuit chip. The PCDTE includes an instruction memory that receives and stores instructions provided on a chip interface, and a configuration memory that receives and stores configuration values provided on the chip interface. The PCDTE also includes a controller that configures a plurality of address counters and data registers in response to the configuration values. The controller also executes the instructions, wherein read/write addresses and write data are retrieved from the counters in response to the instructions. The retrieved read/write addresses and write data are used to access a memory under test. Multiple ports of the memory under test may be simultaneously accessed. Multiple instructions may be linked. The instructions may specify special counting functions within the counters and/or specify integrated (linked) counters.

Abstract: The present disclosure provides an emulator mapping process on a system-on-a-chip (SoC) for debugging. The implementation reduces manual intervention and makes the emulation mapping process very generic and technology independent and hence it reduces overall project cycle time. In the present disclosure, the SoCs containing analog delay locked loops are made suitable for emulation by configuring analog delay locked loop module in parallel with a synthesizable delay logic module. Further, selection logic is provided to select any one of the module at a time.

Abstract: A method, system, and computer program product are used for enhancing quality of contact lists for direct marketing campaigns. An embodiment of the method includes receiving a contact list that includes a plurality of customer profiles, and performing at least one of a counts verification check, a criteria outlier check, a data values check, and an output file check on the contact list. The method performs the aforementioned checks based at least partially on one or more quality check (QC) parameters. Further, the method includes generating a QC report that includes error statistics pertaining to at least one of the aforementioned checks. The method further generates an exceptions report based on the QC report and the QC parameters, and modifies the QC parameters based on the exceptions report.

Abstract: A system and method allow a user to extract the set of customizations performed on an application and use these to estimate the time and effort and cost of (a) migrating to a new version of the application and/or (b) consolidating systems. The user can browse the extracted data and select configuration elements for re-use. After downloading the one or more configurations and comparing them, the user selects elements of the configurations for re-use. The first step is to scan one or more application systems and extract the configuration data using a surveyor. The method according to the invention automatically identifies configuration differences. The user then selects configuration elements for re-use. A graphic user interface (GUI) can be provided which allows the user to make these selections by dragging and dropping selected elements to a “To Be” configuration. The selected configurations are then uploaded and installed on an instance of the application.

Abstract: A method for configuring a software package for an enterprise includes gathering desired To-be configuration requirements for a software package through at least one questionnaire; gathering current As-is raw data for the enterprise; displaying the To-Be configuration requirements and As-is raw data; comparing the To-Be configuration requirements and As-is raw data; selecting final To-Be configuration requirements; and generating and executing configuration code for the software package to pre-configure the software package with the final To-Be configuration requirements.

Abstract: An integrated circuit may include a packet decoder to receive serial data and to decode JTAG signals from the packets received. A JTAG processor may test the electrical circuitry dependent on the JTAG signals decoded. In a further embodiment, a test system may include a library of selectable JTAG routines. An encoder may encode a signal with serial data representative of sequential JTAG signals for at least one of the selectable JTAG routines. In a method of testing, the integrated circuit may receive the serial data signal at a predetermined terminal. A portion of the serial data may be examined to determine the presence of a predefined signature key. JTAG data may then be parsed from the serial data and tests performed based on the parsed JTAG data.

Abstract: Methods of operating an instruction cache memory in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the instruction cache memory include a number of sets (nsets), where each of the sets comprise a number of ways (nways). One or more first instructions may be executed to load one or more instructions into a first way of the instruction cache memory. One or more second instructions may be executed to lock the first way of the instruction cache memory. A sequence of instructions may be executed including the one or more instructions loaded in the first way of the instruction cache memory, and it may be predetermined that the one or more instructions loaded in the first way of the instruction cache memory will executed without retrieving the one or more instructions from the memory during execution of the sequence of instructions.

Abstract: Methods of maintaining cache coherency of a virtual cache memory system in a data processing system are disclosed. The entries of the virtual cache memory include physical address information and logical address information. A memory access operation may be initiated on one or more predetermined memory locations based on physical address information. A determination may be made if the memory access operation may involve cache coherent memory. If the memory access operation may involve cache coherent memory, then a cache coherency command may be issued that contains physical address information of the memory access operation. Based on the cache coherency command and the physical address information, a determination may be made if there is a match between the physical address information of the memory access operation and the physical address information stored in the virtual cache.

Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted.

Abstract: Methods of managing a cache memory system in a data processing system are disclosed. The data processing system executes instructions and stores and receives data from a memory having locations in a memory space. The entries of the cache memory are in locations in a register space separate from the memory space. A first instruction that operates only on locations in a register space but not on locations in memory space may be executed to obtain address information from at least one entry of the cache memory. The obtained address information be compared with target address information. If the comparison between the obtained address information and the target address information results in a correspondence, then a first operation may be performed on the entry of the cache memory. If the comparison between the obtained address information and the target address information does not result in a correspondence, then the fit first operations not performed on the entry of the cache memory.

Abstract: Methods and an apparatus for buffering write operations are disclosed. In one embodiment, a processing system bursts data to a bus. The processing system includes a memory cache, a write buffer unit, and a control unit. The memory cache produces an address and data. Included in the write buffer unit are a plurality of data locations coupled to the memory cache. The control unit directs the first data to any of the plurality of data locations.

Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted.

Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

Abstract: Methods of widening the permission for a memory access in a data processing system having a virtual cache memory and a translation lookaside buffer are disclosed. A memory access operation is initiated on a predetermined memory location based on logical address information and permission information associated with the memory access operation. The virtual cache memory is accessed and a determination may be made if there is a match between logical address information of the memory access operation and logical address information stored in the entries of the virtual cache. In the event of a match, then a determination may be made based on the permission information of the memory access operation and the permission information of the particular entry of the virtual cache memory as to whether the memory access operation is permitted.