Abstract: A sensory evaluation device, and methods of using the same, for the evaluation of the efficacy of odor-absorbing compositions, particularly animal litters. The sensory evaluation device includes a first chamber containing one odor-absorbing composition suitable for use as an animal litter coupled to a second chamber containing a second odor-absorbing composition suitable for use as an animal litter. Each odor-absorbing composition is dosed with an odor-emitting substance, preferably colored such that the dosing is visible. Each chamber contains a vapor-permeable barrier, which is capable of communication with the ambient environment. The vapor-permeable barriers are protected from the ambient environment by vapor-permeable barrier protectors, which are removably coupled to the vapor-permeable barriers. More than one sensory evaluation device may be comparatively used by a single user at one time.

Abstract: A packaged integrated circuit which includes a die 700 having a surface and corners separated by edges. The die surface includes depressions 600, 720 so that mold compound 114 covering the die surface fills the depressions. The filling of the depressions in the die surface enhances the adhesion of the mold compound to the die. The die can include bond pads 714, in which case the depressions can take the form of slots 720 in the bond pads. In addition, the depressions can take the form of trenches 600 at the surface of the die in a dielectric layer 703. The trenches can be at the die corners and along the die edges.

Abstract: An isolated DNA sequence set forth in SEQ ID NO: 32, which is differentially expressed in apical buds of plant Caragana jubata (Pall.) under freezing conditions, is disclosed.

Abstract: A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availability. To maintain transparency to service users and service applications, service users are located on a first network and production servers are located on a second network. The service appliance assumes the addresses of the service users on the second network and the addresses of the production servers on the first network. Thus, the service appliance obtains all network traffic sent between the production server and service users. While the service application is operating correctly, the service appliance forwards network traffic between the two networks using various network layers.

Abstract: A service appliance is installed between a production server running a service applications and service users. Upon being connected with the production server, the service appliance contacts the production server and/or service application and automatically replicates the service data from the service application. As additional service data is added to or modified by the service application of the production server, the service appliance automatically updates its replica of the data. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availibility using the replica of the data. When an operational production server is connected with the service appliance, the service appliance can automatically copy its service data to the service application of the operational production server. The operational production server can be the same as the original production server or a new production server.

Abstract: A service appliance can be installed between one or more production servers running service applications and service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain service availibility. The service appliance is capable of providing the service using a service application that is differently configured or even a different application than the service applications of the production server. The service appliance may include hardware and/or software to monitor, repair, maintain, and update the service application and other associated software applications and components of service appliance. The service appliance may be configured to have a locked state that prevents local running of additional applications other than those provided for prior to entering the locked state, limiting local and remote user administration of and operational control of the operating system and service application.

Abstract: A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. The service appliance replicates the service data of service applications and monitors the service application. If the service appliance detects that the service application has failed or is about to fail, the service appliance takes control of the service. Using the replica of the service data, the service appliance responds to service users in essentially the same manner as a fully operational service application and production server and updates its replica of the service data as needed. When the service appliance detects that the service application has resumed functioning, the service appliance automatically synchronizes the data of the service application of the production server with the service appliance's data and returns control of the service to the service application and its production server.

Abstract: A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

Abstract: A method for performing high-level synthesis (HLS) of a digital design includes a first phase for performing transformations on a behavioral description of the design, and a second phase for selecting a transformation from a plurality of transformations for transforming the behavioral description. The method further includes a third phase for implementing the transformed behavioral description using lower level primitives, and a fourth phase for generating implementation codes for the design.

Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.

Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.

Abstract: A high power unipolar FET switch has an N− drift layer; a layer of metal contacts the drift layer via an ohmic contact to provide a drain connection for the FET. Each switch cell has a pair of trenches recessed into the drift layer and separated by a mesa region. Oxide layers line the walls and bottom of each trench, which are each filled with a conductive material; the conductive material in each trench is connected together to provide a gate connection for the FET. A shallow P region extends from the bottom of each trench into the drift layer and around the trench corners. A layer of metal contacts the mesa region via an ohmic contact to provide a source connection for the FET. The structure preferably operates as a “normally-off” device, with the potentials created by the work function difference between the conductive material and the N− mesa region completely depleting the mesa region.

Abstract: A high power rectifier device has an − drift layer on an N+ layer. A number of trench structures are recessed into the drift layer opposite the N+ layer; respective mesa regions separate each pair of trenches. Each trench structure includes oxide side-walls and an oxide bottom, and is filled with a conductive material. A metal layer contacts the trench structures and mesa regions, forming Schottky contacts at the metal-mesa interface. Shallow P regions extend from the bottom of each trench into the drift layer. Forward conduction occurs when the Schottky contact's barrier height is overcome. When reversed-biased, depletion regions form around the shallow P regions and the oxide side-walls which provide potential barriers across the mesa regions that shield the Schottky contacts from high electric fields, providing a high reverse blocking voltage and reducing reverse leakage current.

Abstract: A system and method for system and circuit level design modeling and simulation using the C++ programming language. Program interfaces in a behavior-less base class are provided to allow a circuit designer to model hardware blocks using user processes in C++. The present invention provides for the manipulation of software user processes that represent the behavior of circuit blocks. C++ is advantageous because it is a familiar language for many designers in the computer industry and therefore requires a smaller learning curve. The novel interface provides an efficient implementation of reactivity (waiting and watching) and concurrency (signals and processes) allowing designers to use C++ to model mixed hardware-software systems with a C++ compiler and a library of the present invention without the need of a complex event-driven run-time kernel, often required in other hardware description languages (HDLs).

Abstract: A controller structure template (60) and method (10) of using the controller structure template (60) for designing a controller structure is provided. The method includes providing (11) a behavioral specification, scheduling, allocating, and binding the behavioral specification (12), dividing (13) the list of statements into statement blocks, clustering (14) the list of statements from each statement block, mapping (15) each statement block into a control block, and mapping (17) each cluster into a control element. The steps of mapping (15 and 17) are performed using a controller structure template (60), which includes a control element template (62), merging logic circuit (63), detection circuit (64), branching logic (67).

Abstract: A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.

Abstract: A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16).

Abstract: An Hardware Description Language (HDL) description file (12) is updated without requiring complete re-assignment of all tokens associated with the HDL statements. The design information is maintained as attributes assigned to the tokens (14). The tokens map onto a block diagram (16). As part of an update to the HDL text file (34), the tokens are compared to see which ones if any have changed. The text lines are compared from left-to-right and right-to-left searching for changes in the text file and associated changes in token mapping (36, 38). All tokens inclusive between the left-most change and right-most change is considered to be different. New tokens are assigned and mapped into the block diagram for the HDL elements that change (40). The mapping of old tokens are removed from the block diagram (42). The mappings from token that did not change are maintained (44).

Abstract: Generating delay targets for creating a multilevel hierarchical circuit design by providing a hierarchical design description and delay constraints of the circuit design; generating a net measure for each net and macro cell of the circuit design, and generating an abstract delay model for each macro cell of the circuit design based on the design description, wherein net measure is the estimated resistive-capacitive delay of a net derived from the estimated length of the net based on area-driven design, and an abstract delay model is a description of delays through a macro cell; generating delay targets for the nets and macro cells based on the net measures, the abstract delay models and the delay constraints; and creating the circuit design based on the delay targets.

Abstract: A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten t