Abstract: A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16).

Abstract: An Hardware Description Language (HDL) description file (12) is updated without requiring complete re-assignment of all tokens associated with the HDL statements. The design information is maintained as attributes assigned to the tokens (14). The tokens map onto a block diagram (16). As part of an update to the HDL text file (34), the tokens are compared to see which ones if any have changed. The text lines are compared from left-to-right and right-to-left searching for changes in the text file and associated changes in token mapping (36, 38). All tokens inclusive between the left-most change and right-most change is considered to be different. New tokens are assigned and mapped into the block diagram for the HDL elements that change (40). The mapping of old tokens are removed from the block diagram (42). The mappings from token that did not change are maintained (44).

Abstract: Generating delay targets for creating a multilevel hierarchical circuit design by providing a hierarchical design description and delay constraints of the circuit design; generating a net measure for each net and macro cell of the circuit design, and generating an abstract delay model for each macro cell of the circuit design based on the design description, wherein net measure is the estimated resistive-capacitive delay of a net derived from the estimated length of the net based on area-driven design, and an abstract delay model is a description of delays through a macro cell; generating delay targets for the nets and macro cells based on the net measures, the abstract delay models and the delay constraints; and creating the circuit design based on the delay targets.

Abstract: A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten t