Patents by Inventor Rajesh Katkar

Rajesh Katkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bonded structures
    Patent number: 10879207
    Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
  • Bonded structures
    Patent number: 10879210
    Abstract: A bonded structure can include a first element having a first interface feature and a second element having a second interface feature. The first interface feature can be bonded to the second interface feature to define an interface structure. A conductive trace can be disposed in or on the second element. A bond pad can be provided at an upper surface of the first element and in electrical communication with the conductive trace. An integrated device can be coupled to or formed with the first element or the second element.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
  • SEALED BONDED STRUCTURES AND METHODS FOR FORMING THE SAME
    Publication number: 20200395321
    Abstract: A bonded structure is disclosed. The bonded structure includes a first element that has a front side and a back side that is opposite the front side. The first element has a first conductive pad and a first nonconductive field region at the front side of the first element. The bonded structure also includes a second element that has a second conductive pad and a second nonconductive field region at a front side of the second element. The second conductive pad is bonded to the first conductive pad along an interface structure. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The bonded structure further includes an elongate conductive structure that extends from the back side of the first element to the interface structure. The elongate conductive structure provides an effectively closed profile around the integrated device.
    Type: Application
    Filed: April 3, 2020
    Publication date: December 17, 2020
    Inventors: Rajesh Katkar, Arkalgud R. Sitaram, Laura Wills Mirkarimi
  • Symbiotic Network On Layers
    Publication number: 20200387471
    Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
    Type: Application
    Filed: April 7, 2020
    Publication date: December 10, 2020
    Applicant: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Rajesh Katkar
  • LOW TEMPERATURE BONDED STRUCTURES
    Publication number: 20200381389
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Cyprian Emeka UZOH, Jeremy Alfred THEIL, Liang WANG, Rajesh KATKAR, Guilian GAO, Laura Wills MIRKARIMI
  • Head mounted viewer for AR and VR scenes
    Patent number: 10852545
    Abstract: An optical device comprising: an image layer including variable transparency pixels and display pixels and a lens layer including variable lens pixels.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: December 1, 2020
    Assignee: Xcelsis Corporation
    Inventors: Ilyas Mohammed, Rajesh Katkar, Belgacem Haba
  • Contact structures with porous networks for solder connections, and methods of fabricating same
    Patent number: 10849240
    Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen, Cyprian Emeka Uzoh
  • Image sensor device
    Patent number: 10847562
    Abstract: An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 24, 2020
    Assignee: Invensas Corporation
    Inventor: Rajesh Katkar
  • Tall and fine pitch interconnects
    Patent number: 10818629
    Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 27, 2020
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • PROTECTIVE ELEMENTS FOR BONDED STRUCTURES
    Publication number: 20200328162
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Belgacem Haba, Javier A. DeLaCruz, Rajesh Katkar, Arkalgud Sitaram
  • WAFER-LEVEL BONDING OF OBSTRUCTIVE ELEMENTS
    Publication number: 20200328165
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 15, 2020
    Inventors: Javier A. DeLaCruz, Rajesh Katkar
  • PROTECTIVE ELEMENTS FOR BONDED STRUCTURES
    Publication number: 20200328164
    Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over at least a portion of the active circuitry. The obstructive material can be configured to obstruct external access to the active circuitry. The bonded structure can include a disruption structure configured to disrupt functionality of the at least a portion of the active circuitry upon debonding of the protective element from the semiconductor element.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
  • Remote optical engine for virtual reality or augmented reality headsets
    Patent number: 10802285
    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: October 13, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • OVER AND UNDER INTERCONNECTS
    Publication number: 20200321275
    Abstract: Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventors: Belgacem Haba, Stephen Morein, Ilyas Mohammed, Rajesh Katkar, Javier A. Delacruz
  • Low temperature bonded structures
    Patent number: 10790262
    Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: September 29, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Jeremy Alfred Theil, Liang Wang, Rajesh Katkar, Guilian Gao, Laura Wills Mirkarimi
  • 3D NAND—high aspect ratio strings and channels
    Patent number: 10784282
    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: September 22, 2020
    Assignee: Xcelsis Corporation
    Inventors: Rajesh Katkar, Xu Chang, Belgacem Haba
  • DIRECT-BONDED LED ARRAYS AND APPLICATIONS
    Publication number: 20200235085
    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Invensas Corporation
    Inventors: Min Tao, Liang Wang, Rajesh Katkar, Cyprian Emeka Uzoh
  • BONDED STRUCTURES
    Publication number: 20200227367
    Abstract: A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 16, 2020
    Inventors: Belgacem Haba, Rajesh Katkar, Ilyas Mohammed, Javier A. DeLaCruz
  • 3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS
    Publication number: 20200203368
    Abstract: Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
    Type: Application
    Filed: July 9, 2019
    Publication date: June 25, 2020
    Applicant: Xcelsis Corporation
    Inventors: Rajesh Katkar, Xu Chang, Belgacem Haba
  • STACKED ARCHITECTURE FOR THREE-DIMENSIONAL NAND
    Publication number: 20200203316
    Abstract: Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.
    Type: Application
    Filed: July 26, 2019
    Publication date: June 25, 2020
    Applicant: Xcelsis Corporation
    Inventors: Stephen Morein, Javier A. Delacruz, Xu Chang, Belgacem Haba, Rajesh Katkar