Patents by Inventor Rajesh Poornachandran

Rajesh Poornachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12079665
    Abstract: Systems, apparatuses and methods may provide for technology that automatically determines a first proposed change to an existing resource allocation associated with a first application in a first node, wherein the first proposed change is determined at least partially based on a requested resource allocation associated with a pending application and a first tolerance associated with the first application. The technology may also issue the first proposed change to the first application and automatically conduct the first proposed change if the first application accepts the first proposed change.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: September 3, 2024
    Assignee: Intel Corporation
    Inventors: Kaushik Balasubramanian, Rajesh Poornachandran, Karan Puttannaiah
  • Publication number: 20240281252
    Abstract: Various examples relate to an apparatus, device, method, and computer program for extending instructions supported by a processor. The apparatus is configured to identify at least a part of a computer program targeting an instruction unsupported by a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor. The apparatus is configured to extend the instructions supported by the processor, based on the targeted unsupported instruction. The apparatus is configured to execute the computer program.
    Type: Application
    Filed: September 23, 2022
    Publication date: August 22, 2024
    Inventors: Mingqiu SUN, Vincent ZIMMER, Rajesh POORNACHANDRAN, Gopinatth SELVARAJE
  • Publication number: 20240273120
    Abstract: Systems, apparatuses and methods include technology that identifies first data that is autonomously generated, where the first data is associated with a first source. The technology may further determine that the first data is to be marked with an indication that the first data is associated with the first source, generate an identifier associated with the first data based on the first data being determined to be marked, where the identifier indicates that the first data is associated with the first source, and store the identifier to an entry in a storage that is remotely accessible.
    Type: Application
    Filed: March 14, 2024
    Publication date: August 15, 2024
    Inventors: Francesc Guim Bernat, Karthik Kumar, Akhilesh S. Thyagaturu, Marcos Carranza, Rajesh Poornachandran
  • Patent number: 12063280
    Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: August 13, 2024
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Vincent Zimmer, Subrata Banik, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Patent number: 12056906
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: August 6, 2024
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Publication number: 20240248965
    Abstract: Various examples relate to apparatuses, devices, methods, and non-transitory machine-readable storage media for presenting content and for a node of a blockchain network. An apparatus for presenting content is to obtain the content, obtain, from at least one decentralized application referenced by the content, at least one license for using the content, and present the content in accordance with the at least one license.
    Type: Application
    Filed: September 26, 2023
    Publication date: July 25, 2024
    Inventors: Rajesh POORNACHANDRAN, Marcos CARRANZA
  • Publication number: 20240249284
    Abstract: Various examples of the present disclosure relate to methods, apparatuses, devices, and computer programs for peers of a blockchain network. A method for distributing tasks to Web3 peers of a blockchain network comprises identifying, during execution of a smart contract, a plurality of tasks to be performed by one or more peers of the blockchain network, determining capabilities of the peers of the blockchain network, wherein at least one capability of at least one peer of the blockchain network is unlocked as an on-demand unlock of the capability at the respective peer, and distributing the plurality of tasks to the one or more peers based on the capabilities of the peers of the blockchain network.
    Type: Application
    Filed: September 29, 2023
    Publication date: July 25, 2024
    Inventors: Rajesh POORNACHANDRAN, Francesc GUIM BERNAT, Marcos CARRANZA, Cesar MARTINEZ-SPESSOT, Mario Jose DIVAN KOLLER
  • Publication number: 20240248633
    Abstract: Various examples of the present disclosure relate to apparatuses, devices, methods, and computer programs for providing and processing information characterizing a non-uniform memory architecture. An apparatus for a computer system comprises processing circuitry to determine a presence of one or more memory devices connected to at least one processor of the computer system via a serial communication-based processor-to-memory interface, the one or more memory devices being part of a non-uniform memory architecture used by the computer system, determine at least one characteristic for the one or more memory devices by estimating or measuring a performance of the one or more memory devices as observed by the at least one processor, and provide information on the at least one characteristic of the one or more memory devices as part of information characterizing the non-uniform memory architecture.
    Type: Application
    Filed: September 29, 2023
    Publication date: July 25, 2024
    Inventors: Francesc GUIM BERNAT, Karthik KUMAR, Marcos CARRANZA, Rajesh POORNACHANDRAN, Thomas WILLHALM
  • Patent number: 12047357
    Abstract: Embodiments described herein are generally directed to a transparent and adaptable mechanism for performing secure application communications through sidecars. In an example, a set of security features is discovered by a first sidecar of a first microservice of multiple microservices of an application. The set of security features are associated with a device of multiple devices of a set of one or more host systems on which the first microservice is running. Information regarding the set of discovered security features is made available to the other microservices by the first sidecar by sharing the information with a discovery service accessible to all of the microservices. A configuration of a communication channel through which a message is to be transmitted from a second microservice to the first microservice is determined by a second sidecar of the second microservice by issuing a request to the discovery service regarding the first microservice.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Cesar Martinez-Spessot, Marcos Carranza, Lakshmi Talluru, Mateo Guzman, Francesc Guim Bernat, Karthik Kumar, Rajesh Poornachandran, Kshitij Arun Doshi
  • Publication number: 20240232622
    Abstract: Apparatus, articles of manufacture, and methods for managing processing units are disclosed. An example apparatus includes first processor circuitry to implement a central processing unit and second processor circuitry to perform at least one of first operations, second operations or third operations to obtain a resource request associated with a first workload; determine if a processing resource of a programmable network device is available to perform processing for the workload; determine if a second workload can be migrated from execution on the programmable network device; based on the determination that the second workload can be migrated, cause the second workload to be migrated; and cause the first workload to execute on the processing resource of the programmable network device.
    Type: Application
    Filed: June 23, 2022
    Publication date: July 11, 2024
    Inventors: Rajesh Poornachandran, Kaushik Balasubramanian, Karan Puttannaiah
  • Publication number: 20240231924
    Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to identify a processing flow pattern of a large language model, LLM, wherein the LLM is executed on a processor circuitry comprising a plurality of processor cores and wherein the processing flow pattern comprising a plurality of processing phases. The machine-readable instructions further comprise instructions to identify a processing phase of the LLM from the processing flow pattern. The machine-readable instructions further comprise instructions to allocate processing resources to the processor circuitry based on the identified processing phase of the LLM.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 11, 2024
    Inventors: Sharanyan SRIKANTHAN, Karthik KUMAR, Francesc GUIM BERNAT, Rajesh POORNACHANDRAN, Marcos CARRANZA
  • Publication number: 20240231801
    Abstract: The technology disclosed herein includes getting a system update configuration for managing updating of at least one of a software component and a firmware component of a computing system powered by a battery; determining an estimated system update time of usage of the battery to update the at least one of the software component and the firmware component based at least in part on the system update configuration; updating the at least one of the software component and the firmware component when resource requirements of the system update configuration are met and the estimated system update time is less than or equal to a minimum remaining time of usage of the battery; and deferring the updating when the resource requirements of the system update configuration are not met or the estimated system update time is greater than the minimum remaining time of usage of the battery.
    Type: Application
    Filed: May 26, 2022
    Publication date: July 11, 2024
    Applicant: Intel Corporation
    Inventors: Subrata BANIK, Rajesh POORNACHANDRAN, Vincent ZIMMER, Utkarsh Y. KAKAIYA
  • Publication number: 20240223611
    Abstract: The technology described herein includes determining a security quality of service (Qos) profile matching configuration attributes of a first computing system, generating an interdependency flow graph based at least in part on the security QoS profile and the configuration attributes, generating a recommended configuration for the first computing system from the interdependency flow graph, and sending the recommended configuration to a second computing system.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Rajesh Poornachandran, Ned M. Smith, Sunil K. Cheruvu
  • Publication number: 20240214390
    Abstract: The technology described herein includes receiving a first reference integrity manifest (RIM) and a first proto-RIM from a first endorser, the first endorser asserting authority, by the first RIM and the first proto-RIM, to supply first attestation reference values for a computing device; storing the first proto-RIM in a RIM transparency database; notarizing the first proto-RIM; and providing the first RIM and the notarized first proto-RIM to a verifier of the computing device.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Ned M. Smith, Rajesh Poornachandran, Sunil K. Cheruvu
  • Publication number: 20240195635
    Abstract: The technology described herein includes a plurality of intellectual property (IP) blocks; and a host IP block, the host IP block including a primary root of trust (RoT) IP block (PRIB) coupled to the plurality of IP blocks, to receive a request from a computing system to establish a secure communications session with a selected one of a plurality of intellectual property (IP) blocks, authenticate and attest the computing system, sign evidence of the PRIB with a PRIB key, send the signed evidence of the PRIB to the computing system, and establish the secure communications session between the computing system and the selected IP block if the PRIB is trusted by the computing system based at least in part on the signed evidence of the PRIB.
    Type: Application
    Filed: December 12, 2022
    Publication date: June 13, 2024
    Applicant: Intel Corporation
    Inventors: Kshitij Doshi, Ned M. Smith, Rajesh Poornachandran, Sunil K. Cheruvu, David W. Palmer
  • Publication number: 20240171657
    Abstract: A computing node in an edge computing network includes a network interface card (NIC), memory storing a plurality of digital object representations of a corresponding plurality of participating entities, and processing circuitry. The processing circuitry detects a message from a participating entity of the plurality. The message is received via the NIC and is associated with a messaging service of the edge computing network. The message is mapped to a service class of a plurality of available service classes based on a service request associated with the message. The message is processed to extract one or more characteristics of the service request. A digital object representation of the plurality of digital object representations is updated based on the one or more characteristics of the service request, the digital object representation corresponding to the participating entity.
    Type: Application
    Filed: June 25, 2021
    Publication date: May 23, 2024
    Inventors: Vesh Raj Sharma Banjade, Kathiravetpillai Sivanesan, Hassnaa Moustafa, Suman A. Sehra, Satish Chandra Jha, Arvind Merwaday, S M Iftekharul Alam, Francesc Guim Bernat, Rajesh Poornachandran, Xin Zhang, Rony Ferzli, Leonardo Gomes Baltar
  • Publication number: 20240152421
    Abstract: An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to receive a request from a virtual machine to execute a task, receive a service-level agreement, SLA, from the virtual machine indicating a desired feature of scanning a computing resource to execute the task for errors, and scan the computing resource for errors based on the SLA.
    Type: Application
    Filed: September 29, 2023
    Publication date: May 9, 2024
    Inventors: Rajesh POORNACHANDRAN, Kaushik BALASUBRAMANIAN, Karan PUTTANNAIAH
  • Publication number: 20240143329
    Abstract: Various examples relate to an apparatus, device, method, and computer program for extending instructions sup-ported by a processor. The apparatus is configured to identify at least a part of a computer program targeting an instruction unsupported by a pre-defined set of instructions of an Instruction Set Architecture (ISA) of the processor. The apparatus is configured to extend the instructions supported by the processor, based on the targeted unsupported instruction. The apparatus is configured to execute the computer program.
    Type: Application
    Filed: September 23, 2022
    Publication date: May 2, 2024
    Inventors: Mingqiu SUN, Vincent ZIMMER, Rajesh POORNACHANDRAN, Gopinatth SELVARAJE
  • Publication number: 20240143376
    Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to receive a request of a virtual machine to access a resource of a network node, determine whether a number of available virtual functions associated to the resource falls below a predefined threshold and, if it is determined that the number of available virtual functions falls below the predefined threshold, emulate and/or para virtualize a physical function associated to the resource. The machine-readable instructions further comprise instructions to provide access to the resource via the emulated and/or para virtualized physical function for the virtual machine.
    Type: Application
    Filed: June 19, 2023
    Publication date: May 2, 2024
    Inventors: Rajesh POORNACHANDRAN, Karunakara KOTARY, Arun Kumar SINGH
  • Publication number: 20240143341
    Abstract: It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions comprise instructions to determine one or more configurable firmware variables of a computing system based on performance analysis data of the computing system executing a workload. The machine-readable instructions further comprise instructions to set the determined one or more configurable firmware variables of the computing system based on reference data. The machine-readable instructions further comprise instructions to control the computing system to apply the set firmware variables during run-time.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 2, 2024
    Inventors: Rajesh POORNACHANDRAN, Vincent J. ZIMMER, Rajkumar KATTUR CHINNUSAMY, Mallikarjuna CHILAKALA, Sreekanth YALACHIGERE, Markus FLIERL, Brendan GREGG