Patents by Inventor Rajesh Poornachandran

Rajesh Poornachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230102279
    Abstract: Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
    Type: Application
    Filed: September 25, 2021
    Publication date: March 30, 2023
    Inventors: Menachem ADELMAN, Robert VALENTINE, Dan BAUM, Amit GRADSTEIN, Simon RUBANOVICH, Regev SHEMY, Zeev SPERBER, Alexander HEINECKE, Christopher HUGHES, Evangelos GEORGANAS, Mark CHARNEY, Arik NARKIS, Rinat RAPPOPORT, Barukh ZIV, Yaroslav POLLAK, Nilesh JAIN, Yash AKHAURI, Brinda GANESH, Rajesh POORNACHANDRAN, Guy BOUDOUKH
  • Publication number: 20230093493
    Abstract: Examples of the present disclosure relate to an apparatus, device, method, and computer program for configuring a processing device, and to a computer system comprising such an apparatus or device. The apparatus or device is configured to obtain information on a failure related to a component of the processing device, with the failure having occurred at runtime of the processing device, determine information on a microcode update to be applied to the processing device to remedy the failure related to the component, and configure the processing device to apply the microcode update.
    Type: Application
    Filed: September 30, 2022
    Publication date: March 23, 2023
    Inventors: Rajesh POORNACHANDRAN, Kshitij Arun DOSHI, Vinayak HONKOTE, Vincent ZIMMER, Subrata BANIK
  • Publication number: 20230037609
    Abstract: Examples described herein relate to an interface and a network interface device coupled to the interface and comprising circuitry to: control power utilization by a first set of one or more devices based on power available to a system that includes the first set of one or more devices, wherein the system is communicatively coupled to the network interface and control cooling applied to the first set of one or more devices.
    Type: Application
    Filed: September 28, 2022
    Publication date: February 9, 2023
    Inventors: Paniraj GURURAJA, Navneeth JAYARAJ, Mahammad Yaseen Isasaheb MULLA, Nitesh GUPTA, Hemanth MADDHULA, Laxminarayan KAMATH, Jyotsna BIJAPUR, Delraj Gambhira DAMBEKANA, Vikrant THIGLE, Amruta MISRA, Anand HARIDASS, Rajesh POORNACHANDRAN, Krishnakumar VARADARAJAN, Sudipto PATRA, Nikhil RANE, Teik Wah LIM
  • Patent number: 11570264
    Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to: obtain, by a microservice of a service hosted in a datacenter, provisioned credentials for the microservice based on an attestation protocol; generate, for a task performed by the microservice, provenance metadata for the task, the provenance metadata including identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and operating state of a sidecar of the microservice during the task; encrypt the provenance metadata with the provisioned credentials for the microservice; and record the encrypted provenance metadata in a local blockchain of provenance metadata maintained for the hardware resource executing the task and the microservice.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 31, 2023
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Vincent Zimmer, Subrata Banik, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Patent number: 11561868
    Abstract: Embodiments described herein are generally directed to intelligent management of microservices failover. In an example, responsive to an uncorrectable hardware error associated with a processing resource of a platform on which a task of a service is being performed by a primary microservice, a failover trigger is received by a failover service. A secondary microservice is identified by the failover service that is operating in lockstep mode with the primary microservice. The secondary microservice is caused by the failover service to takeover performance of the task in non-lockstep mode based on failover metadata persisted by the primary microservice. The primary microservice is caused by the failover service to be taken offline.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: Rajesh Poornachandran, Marcos Carranza, Kshitij Arun Doshi, Francesc Guim Bernat, Karthik Kumar
  • Publication number: 20230013452
    Abstract: System and techniques for an environmental control loop are described herein. A device for an environmental control loop can include a memory including instructions and processing circuitry that when in operation, can be configured by the instructions to receive environmental sensor data from a first component in a set of heterogeneous components installed in an environment with a controller. The environmental sensor data can indicate a service level value sensed by the first component. The controller can also measure a violation of a service level objective based on comparing the environmental sensor data to a threshold. The controller can also transmit an adjustment to an operating parameter of a second component of the set of heterogeneous components. The adjustment can be operative to attenuate the violation of the service level objective when implemented by the second component.
    Type: Application
    Filed: September 27, 2022
    Publication date: January 19, 2023
    Inventors: S M Iftekharul Alam, Marcos E. Carranza, Francesc Guim Bernat, Mateo Guzman, Satish Chandra Jha, Cesar Martinez-Spessot, Arvind Merwaday, Rajesh Poornachandran, Vesh Raj Sharma Banjade, Kathiravetpillai Sivanesan, Ned M. Smith, Liuyang Lily Yang, Mario Jose Divan Koller
  • Publication number: 20230018149
    Abstract: Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Applicant: Intel Corporation
    Inventors: Mingqiu Sun, Rajesh Poornachandran, Vincent Zimmer, Gopinatth Selvaraje
  • Patent number: 11557064
    Abstract: Embodiments are generally directed to compression in machine learning and deep learning processing. An embodiment of an apparatus for compression of untyped data includes a graphical processing unit (GPU) including a data compression pipeline, the data compression pipeline including a data port coupled with one or more shader cores, wherein the data port is to allow transfer of untyped data without format conversion, and a 3D compression/decompression unit to provide for compression of untyped data to be stored to a memory subsystem and decompression of untyped data from the memory subsystem.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 17, 2023
    Inventors: Joydeep Ray, Ben Ashbaugh, Prasoonkumar Surti, Pradeep Ramani, Rama Harihara, Jerin C. Justin, Jing Huang, Xiaoming Cui, Timothy B. Costa, Ting Gong, Elmoustapha Ould-ahmed-vall, Kumar Balasubramanian, Anil Thomas, Oguz H. Elibol, Jayaram Bobba, Guozhong Zhuang, Bhavani Subramanian, Gokce Keskin, Chandrasekaran Sakthivel, Rajesh Poornachandran
  • Patent number: 11558265
    Abstract: An apparatus to facilitate telemetry targeted query injection for enhanced debugging in microservices architectures is disclosed. The apparatus includes one or more processors to: identify contextual trace of a previous query recorded in collected data of a service, where microservices of the service responded to the previous query; access an interdependency flow graph representing an architecture and interaction of microservices deployed for a service; retrieve, based on the interdependency flow graph, telemetry data of the microservices corresponding to the contextual trace; identify, based on the telemetry data, an activation profile corresponding to the previous query, the activation profile detailing a response of the microservices to the previous query; compare the activation profile to a correlation profile for the previous query to detect whether an anomaly occurred in the service in response to the previous query; and recommend a modified query based on detection of the anomaly.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 17, 2023
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Marcos Carranza
  • Publication number: 20220413943
    Abstract: interface circuitry to detect a request to obtain a resource request from a workload and processor circuitry including one or more of: at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry, arithmetic and logic circuitry, and one or more registers, the processor circuitry to execute instructions to: determine if resources are available for the workload on an infrastructure processing unit managed system; negotiate with the infrastructure processing unit to determine if an executing workload can be migrated; in response to determining that an executing workload can be migrated, cause the executing workload to be migrated; and cause the workload to execute on the resource.
    Type: Application
    Filed: March 25, 2022
    Publication date: December 29, 2022
    Inventors: Rajesh Poornachandran, Kaushik Balasubramanian, Karan Puttannaiah
  • Publication number: 20220417589
    Abstract: Embodiments of mechanisms for dynamic media content type streaming management for mobile devices are generally described herein. In some embodiments, the mobile device may receive selection input pertaining to generating output from a media file containing at least two of audio data, video data, and closed-captioning data, the selection input selecting at least one of audio, video, and closed-captioning to be output during play of the media content. In some embodiments, the mobile device may generate an audio output as a signal in response to the selection input including audio. In some embodiments, the mobile device may generate a video output as a signal in response to the selection input including video. In some embodiments, the mobile device may generate a closed-captioning output as a signal in response to selection input including closed-captioning.
    Type: Application
    Filed: July 7, 2022
    Publication date: December 29, 2022
    Inventors: Gyan Prakash, Rajesh Poornachandran, Brian J. Hernacki, Kaitlin Murphy, Rita H. Wouhaybi
  • Patent number: 11533316
    Abstract: Systems and techniques for information-centric network namespace policy-based content delivery are described herein. A registration request may be received from a node on an information-centric network (ICN). Credentials of the node may be validated. The node may be registered with the ICN based on results of the validation. A set of content items associated with the node may be registered with the ICN. An interest packet may be received from a consumer node for a content item of the set of content items that includes an interest packet security level for the content item. Compliance of the security level of the node with the interest packet security level may be determined. The content item may be transmitted to the consumer node.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Srikathyayani Srikanteswara, Ravikumar Balakrishnan, Rajesh Poornachandran, Moreno Ambrosin
  • Publication number: 20220382526
    Abstract: Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: INTEL CORPORATION
    Inventors: Mingqiu SUN, Rajesh POORNACHANDRAN, VINCENT J. ZIMMER, Ned M. SMITH, Gopinatth SELVARAJE
  • Patent number: 11509679
    Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., non-transitory physical storage media) to provide trust topology selection for distributed transaction processing in computing environments are disclosed herein. Example distributed transaction processing nodes disclosed herein include a distributed transaction application to process a transaction in a computing environment based on at least one of a centralized trust topology or a diffuse trust topology. Disclosed example distributed transaction processing nodes also include a trusted execution environment to protect first data associated with a centralized trust topology and to protect second data associated with a diffuse trust topology. Disclosed example distributed transaction processing nodes further include a trust topology selector to selectively configure the distributed transaction application to use the at least one of the centralized trust topology or the diffuse trust topology to process the transaction.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Ned Smith, Rajesh Poornachandran
  • Publication number: 20220365813
    Abstract: Examples relate to an apparatus, a device, a method, and a computer program for scheduling an execution of compute kernels on one or more computing devices, and to a computer system comprising such an apparatus or device. The apparatus comprises processing circuitry and interface circuitry. The processing circuitry is configured to determine an impending execution of two or more compute kernels to the one or more computing devices. The processing circuitry is configured to pipeline a data transfer related to the execution of the two or more compute kernels to the one or more computing devices via the interface circuitry.
    Type: Application
    Filed: June 28, 2022
    Publication date: November 17, 2022
    Inventors: Rajesh POORNACHANDRAN, Ben J. ASHBAUGH, Gregory LUECK, James BRODMAN, Simon PENNYCOOK, Michael KINSNER, Roland SCHULZ
  • Publication number: 20220353328
    Abstract: Methods, apparatus, systems and articles of manufacture to dynamically control devices based on distributed data are disclosed. An example apparatus includes a comparator to compare a first measurement measured by a first peer device to a second measurement, the second measurement being measured locally by the apparatus; and an operation adjuster to, when the comparison satisfies a threshold, adjust a measurement protocol of the first peer device.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 3, 2022
    Inventors: Rita Wouhaybi, Rajesh Poornachandran
  • Patent number: 11487517
    Abstract: Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Mingqiu Sun, Rajesh Poornachandran, Vincent J. Zimmer, Ned M. Smith, Gopinatth Selvaraje
  • Publication number: 20220326962
    Abstract: An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 13, 2022
    Inventors: Navneeth JAYARAJ, Richard Marian THOMAIYAR, Ashraf JAVEED, Vikas MISHRA, Rajesh POORNACHANDRAN, Mahammad Yaseen Isasaheb MULLA, Laxminarayan KAMATH, Karunakara KOTARY, Dustin FREDRICKSON
  • Publication number: 20220327267
    Abstract: Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventors: Rajesh POORNACHANDRAN, Michael KINSNER, John FREEMAN, Joseph GARVEY, Artem RADZIKHOVSKYY
  • Publication number: 20220326991
    Abstract: Examples relate to an apparatus, a device, a method, and a computer program for controlling the execution of a computer program by a computer system comprising two or more different Processing Units (XPUs), and to a corresponding computer system. The apparatus comprises processing circuitry configured to obtain the computer program, wherein at least a portion of the computer program is based on one or more compute kernels to be executed by the two or more different XPUs. The processing circuitry is configured to determine, for each XPU, an energy-related metric for executing the one or more compute kernels on the respective XPU. The processing circuitry is configured to assign the execution of the one or more compute kernels to the two or more different XPUs based on the respective energy-related metric.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventor: Rajesh POORNACHANDRAN