Patents by Inventor Rajesh Poornachandran

Rajesh Poornachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11558265
    Abstract: An apparatus to facilitate telemetry targeted query injection for enhanced debugging in microservices architectures is disclosed. The apparatus includes one or more processors to: identify contextual trace of a previous query recorded in collected data of a service, where microservices of the service responded to the previous query; access an interdependency flow graph representing an architecture and interaction of microservices deployed for a service; retrieve, based on the interdependency flow graph, telemetry data of the microservices corresponding to the contextual trace; identify, based on the telemetry data, an activation profile corresponding to the previous query, the activation profile detailing a response of the microservices to the previous query; compare the activation profile to a correlation profile for the previous query to detect whether an anomaly occurred in the service in response to the previous query; and recommend a modified query based on detection of the anomaly.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: January 17, 2023
    Assignee: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Marcos Carranza
  • Publication number: 20220413943
    Abstract: interface circuitry to detect a request to obtain a resource request from a workload and processor circuitry including one or more of: at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry, arithmetic and logic circuitry, and one or more registers, the processor circuitry to execute instructions to: determine if resources are available for the workload on an infrastructure processing unit managed system; negotiate with the infrastructure processing unit to determine if an executing workload can be migrated; in response to determining that an executing workload can be migrated, cause the executing workload to be migrated; and cause the workload to execute on the resource.
    Type: Application
    Filed: March 25, 2022
    Publication date: December 29, 2022
    Inventors: Rajesh Poornachandran, Kaushik Balasubramanian, Karan Puttannaiah
  • Publication number: 20220417589
    Abstract: Embodiments of mechanisms for dynamic media content type streaming management for mobile devices are generally described herein. In some embodiments, the mobile device may receive selection input pertaining to generating output from a media file containing at least two of audio data, video data, and closed-captioning data, the selection input selecting at least one of audio, video, and closed-captioning to be output during play of the media content. In some embodiments, the mobile device may generate an audio output as a signal in response to the selection input including audio. In some embodiments, the mobile device may generate a video output as a signal in response to the selection input including video. In some embodiments, the mobile device may generate a closed-captioning output as a signal in response to selection input including closed-captioning.
    Type: Application
    Filed: July 7, 2022
    Publication date: December 29, 2022
    Inventors: Gyan Prakash, Rajesh Poornachandran, Brian J. Hernacki, Kaitlin Murphy, Rita H. Wouhaybi
  • Patent number: 11533316
    Abstract: Systems and techniques for information-centric network namespace policy-based content delivery are described herein. A registration request may be received from a node on an information-centric network (ICN). Credentials of the node may be validated. The node may be registered with the ICN based on results of the validation. A set of content items associated with the node may be registered with the ICN. An interest packet may be received from a consumer node for a content item of the set of content items that includes an interest packet security level for the content item. Compliance of the security level of the node with the interest packet security level may be determined. The content item may be transmitted to the consumer node.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Srikathyayani Srikanteswara, Ravikumar Balakrishnan, Rajesh Poornachandran, Moreno Ambrosin
  • Publication number: 20220382526
    Abstract: Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Applicant: INTEL CORPORATION
    Inventors: Mingqiu SUN, Rajesh POORNACHANDRAN, VINCENT J. ZIMMER, Ned M. SMITH, Gopinatth SELVARAJE
  • Patent number: 11509679
    Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., non-transitory physical storage media) to provide trust topology selection for distributed transaction processing in computing environments are disclosed herein. Example distributed transaction processing nodes disclosed herein include a distributed transaction application to process a transaction in a computing environment based on at least one of a centralized trust topology or a diffuse trust topology. Disclosed example distributed transaction processing nodes also include a trusted execution environment to protect first data associated with a centralized trust topology and to protect second data associated with a diffuse trust topology. Disclosed example distributed transaction processing nodes further include a trust topology selector to selectively configure the distributed transaction application to use the at least one of the centralized trust topology or the diffuse trust topology to process the transaction.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Ned Smith, Rajesh Poornachandran
  • Publication number: 20220365813
    Abstract: Examples relate to an apparatus, a device, a method, and a computer program for scheduling an execution of compute kernels on one or more computing devices, and to a computer system comprising such an apparatus or device. The apparatus comprises processing circuitry and interface circuitry. The processing circuitry is configured to determine an impending execution of two or more compute kernels to the one or more computing devices. The processing circuitry is configured to pipeline a data transfer related to the execution of the two or more compute kernels to the one or more computing devices via the interface circuitry.
    Type: Application
    Filed: June 28, 2022
    Publication date: November 17, 2022
    Inventors: Rajesh POORNACHANDRAN, Ben J. ASHBAUGH, Gregory LUECK, James BRODMAN, Simon PENNYCOOK, Michael KINSNER, Roland SCHULZ
  • Publication number: 20220353328
    Abstract: Methods, apparatus, systems and articles of manufacture to dynamically control devices based on distributed data are disclosed. An example apparatus includes a comparator to compare a first measurement measured by a first peer device to a second measurement, the second measurement being measured locally by the apparatus; and an operation adjuster to, when the comparison satisfies a threshold, adjust a measurement protocol of the first peer device.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 3, 2022
    Inventors: Rita Wouhaybi, Rajesh Poornachandran
  • Patent number: 11487517
    Abstract: Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers incorporated into multiple computing devices. An apparatus includes a first processor component and first secure controller of a first computing device, where the first secure controller includes: a selection component to select the first secure controller or a second secure controller of a second computing device to compile a task routine based on a comparison of required resources to compile the task routine and available resources of the first secure controller; and a compiling component to compile the task routine into a first version of compiled routine for execution within the first secure controller by the first processor component and a second version for execution within the second secure controller by a second processor component in response to selection of the first secure controller. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: November 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Mingqiu Sun, Rajesh Poornachandran, Vincent J. Zimmer, Ned M. Smith, Gopinatth Selvaraje
  • Publication number: 20220327267
    Abstract: Examples relate to an apparatus, device, method, and computer program for generating logic to be performed by computing circuitry of a computing architecture. The apparatus is configured to determine a performance-critical compute path of a compute kernel to be executed on a plurality of units of computing circuitry of a computing architecture, the compute kernel comprising a plurality of interdependent groups of computational instructions, with the performance-critical compute path being based on a subset of the interdependent groups of computational instructions. The apparatus is configured to determine, for at least one group of computational instructions outside the performance-critical compute path, a reduced clock frequency being lower than a maximally feasible clock frequency of the respective group of computational instructions.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventors: Rajesh POORNACHANDRAN, Michael KINSNER, John FREEMAN, Joseph GARVEY, Artem RADZIKHOVSKYY
  • Publication number: 20220326962
    Abstract: An apparatus is described. The apparatus includes an accelerator having an interface to plug into an electronic system. The accelerator includes a field programmable gate array integrated circuit to perform acceleration, a general purpose processor integrated circuit to execute software related to the acceleration and controller circuitry to dynamically change, without rebooting the general purpose processor integrated circuit, allocation of the accelerator's power budget to the field programmable gate array integrated circuit and the general purpose processor integrated circuit.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 13, 2022
    Inventors: Navneeth JAYARAJ, Richard Marian THOMAIYAR, Ashraf JAVEED, Vikas MISHRA, Rajesh POORNACHANDRAN, Mahammad Yaseen Isasaheb MULLA, Laxminarayan KAMATH, Karunakara KOTARY, Dustin FREDRICKSON
  • Publication number: 20220326991
    Abstract: Examples relate to an apparatus, a device, a method, and a computer program for controlling the execution of a computer program by a computer system comprising two or more different Processing Units (XPUs), and to a corresponding computer system. The apparatus comprises processing circuitry configured to obtain the computer program, wherein at least a portion of the computer program is based on one or more compute kernels to be executed by the two or more different XPUs. The processing circuitry is configured to determine, for each XPU, an energy-related metric for executing the one or more compute kernels on the respective XPU. The processing circuitry is configured to assign the execution of the one or more compute kernels to the two or more different XPUs based on the respective energy-related metric.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventor: Rajesh POORNACHANDRAN
  • Patent number: 11431561
    Abstract: The Internet can be configured to provide communications to a large number of Internet-of-Things (IoT) devices. Devices can be designed to address the need for network layers, from central servers, through gateways, down to edge devices, to grow unhindered, to discover and make accessible connected resources, and to support the ability to hide and compartmentalize connected resources. Network protocols can be part of the fabric supporting human accessible services that operate regardless of location, time, or space. Innovations can include service delivery and associated infrastructure, such as hardware and software. Services may be provided in accordance with specified Quality of Service (QoS) terms. The use of IoT devices and networks can be included in a heterogeneous network of connectivity including wired and wireless technologies.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 30, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ned M. Smith, Keith Nolan, Mark Kelly, Gregory Burns, Michael Nolan, John Brady, Cliodhna Ni Scanaill, Niall Cahill, Thiago Macieira, Zheng Zhang, Glen J. Anderson, Igor Muttik, Davide Carboni, Eugene Ryan, Richard Davies, Toby M. Kohlenberg, Maarten Koning, Jakub Wenus, Rajesh Poornachandran, William C. Deleeuw, Ravikiran Chukka
  • Patent number: 11429496
    Abstract: An apparatus to facilitate data resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store data resiliency logic and one or more processors to execute the data resiliency logic to collect boot critical data from a plurality of platform components and store the data within the non-volatile memory.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Karunakara Kotary, Prashant Dewan, Vincent Zimmer, Rajesh Poornachandran
  • Patent number: 11425111
    Abstract: Various approaches for implementing attestation using an attestation token are described. In an edge computing system deployment, an edge computing device includes an attestable feature (e.g., resource, service, entity, property, etc.) which is accessible from use of an attestation token, by the operations of: obtaining a first instance of a token that provides proof of attestation for an accessible feature of the edge computing device, with the token including data to indicate trust level designations for the feature as attested by an attestation provider; receiving, from a prospective user of the feature, a request to use the feature and a second instance of the token, with the second instance of the token originating from the attestation provider; and providing access to the feature based on a verification of the instances of the token, by using the verification to confirm attestation of the trust level designations for the feature.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, John J. Browne, Kapil Sood, Francesc Guim Bernat, Kshitij Arun Doshi, Rajesh Poornachandran, Tarun Viswanathan, Manish Dave
  • Publication number: 20220222194
    Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Neelam CHANDWANI, Shridhar BENDI, Rajesh VIVEKANANDHAM, Rahul PAL, Eric J. DAHLEN, Antonio J. HASBUN MARIN, Chung-Chi WANG, Qian LI, Hosein NIKOPOUR, Sravanthi KOTA VENKATA, Rajesh POORNACHANDRAN, Udayan MUKHERJEE
  • Publication number: 20220219324
    Abstract: A safety system includes a robot, the robot comprising, a function module, configured to perform a robot function; and a safety module, configured to communicate with the robot, the safety module comprising a stimulus-response tester, configured to send a stimulus of a stimulus-response pair, comprising a stimulus and an expected response to the stimulus, to the robot for processing by the function module; and receive from the function module a response representing the processed stimulus; wherein if a difference between the response and the expected response is within a predetermined range, the safety module is configured to operate according to a first operational mode; and if the difference between the response and the expected response is outside of the predetermined range, the safety module is configured to operate according to a second operational mode.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Vinayak HONKOTE, Rajesh POORNACHANDRAN, Nikhilesh Kumar SINGH
  • Patent number: 11388475
    Abstract: Embodiments of mechanisms for dynamic media content type streaming management for mobile devices are generally described herein. In some embodiments, the mobile device may receive selection input pertaining to generating output from a media file containing at least two of audio data, video data, and closed-captioning data, the selection input selecting at least one of audio, video, and closed-captioning to be output during play of the media content. In some embodiments, the mobile device may generate an audio output as a signal in response to the selection input including audio. In some embodiments, the mobile device may generate a video output as a signal in response to the selection input including video. In some embodiments, the mobile device may generate a closed-captioning output as a signal in response to selection input including closed-captioning.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Gyan Prakash, Rajesh Poornachandran, Brian J. Hernacki, Kaitlin Murphy, Rita H. Wouhaybi
  • Publication number: 20220197678
    Abstract: Apparatus and method for secure instruction set execution, emulation, monitoring, and prevention. A processor embodiment includes registers, evaluator, and execution unit. The registers are to store rules which specify actions to be taken with respect to one or more instructions. The evaluator is to detect a request to execute a first instruction and to evaluate the first instruction based on the rules stored in the one or more registers. The evaluator is further to block execution of the first instruction when a first rule corresponding to the first instruction specifies that execution of the first instruction is prohibited, and to allow execution of the first instruction when there is no rule in the one or more registers specifying that the execution of the first instruction is prohibited. The execution unit is to execute the first instruction when the evaluator allows execution of the first instruction.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Applicant: INTEL CORPORATION
    Inventors: Rajesh Poornachandran, Vincent Zimmer, Prashant Dewan
  • Publication number: 20220197715
    Abstract: An apparatus to facilitate data parallel programming-based transparent transfer across heterogeneous devices is disclosed. The apparatus includes a processor to: identify a change in device status that triggers a device transfer process from an original device, wherein the original device is associated with a queue of an application program of a data parallel programming runtime; identify a new device that is compatible with the original device; migrate at least one of a state or data of the original device to the new device; logically map, without user intervention, the queue to the new device in the data parallel programming runtime; and initiate execution of the application program on the new device using the queue.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Ben J. Ashbaugh, Michael Kinsner, James Brodman, Rajesh Poornachandran