Patents by Inventor Rajesh Sathiyanarayanan

Rajesh Sathiyanarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128091
    Abstract: A method includes providing, within an etch chamber, a base structure including a target layer disposed on a substrate, and an etch mask disposed on the target layer, dry etching, within the etch chamber, the target layer using thionyl chloride to obtain a processed base structure, and after forming the plurality of features. The processed base structure includes a plurality of features and a plurality of openings defined by the etch mask. The method further includes removing the processed base structure from the etch chamber. In some embodiments, the target layer includes carbon. In some embodiments, the dry etching is performed at a sub-zero degree temperature.
    Type: Application
    Filed: July 12, 2023
    Publication date: April 18, 2024
    Inventors: Zhonghua Yao, Qian Fu, Mark J. Saly, Yang Yang, Jeffrey W. Anthis, David Knapp, Rajesh Sathiyanarayanan
  • Publication number: 20230299170
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: August 31, 2022
    Publication date: September 21, 2023
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 11049722
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Publication number: 20200234959
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10615041
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10608097
    Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: March 31, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Seshadri Ganguli, Shih Chung Chen, Rajesh Sathiyanarayanan, Atashi Basu, Lin Dong, Naomi Yoshida, Sang Ho Yu, Liqi Wu
  • Patent number: 10418505
    Abstract: A method including installing solar pods at varying heights on a tower, where a size of each of the solar pods is inversely related its installation height on the tower, each of the solar pods including a transparent ovoid enclosure symmetrical about an axis, and a reflector and a solar cell both contained within the transparent ovoid enclosure, the solar cell positioned at a common focal point of the reflector such that substantially all light reflected by the reflector is directed at the solar cell.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Aveek N. Chatterjee, Kota V. R. M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan
  • Patent number: 10366897
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 10347494
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20190181011
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 13, 2019
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10319596
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20190019874
    Abstract: Film stacks and methods of forming film stacks including a high-k dielectric layer on a substrate, a high-k capping layer on the high-k dielectric layer, an n-metal layer on the high-k capping layer and an n-metal capping layer on the n-metal layer. The n-metal layer having an aluminum rich interface adjacent the high-k capping layer.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 17, 2019
    Inventors: Paul F. Ma, Seshadri Ganguli, Shih Chung Chen, Rajesh Sathiyanarayanan, Atashi Basu, Lin Dong, Naomi Yoshida, Sang Ho Yu, Liqi Wu
  • Patent number: 10170576
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180226257
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 9, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9984883
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Patent number: 9972497
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: May 15, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180096851
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: November 16, 2017
    Publication date: April 5, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20180083116
    Abstract: A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 22, 2018
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170278713
    Abstract: A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Takashi Ando, Mohit Bajaj, Terence B. Hook, Rajan K. Pandey, Rajesh Sathiyanarayanan
  • Publication number: 20170256664
    Abstract: A method including installing solar pods at varying heights on a tower, where a size of each of the solar pods is inversely related its installation height on the tower, each of the solar pods including a transparent ovoid enclosure symmetrical about an axis, and a reflector and a solar cell both contained within the transparent ovoid enclosure, the solar cell positioned at a common focal point of the reflector such that substantially all light reflected by the reflector is directed at the solar cell.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Inventors: Aveek N. Chatterjee, Kota V.R.M. Murali, Ninad D. Sathaye, Rajesh Sathiyanarayanan