Patents by Inventor Rajesh Sundaram

Rajesh Sundaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10541009
    Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 21, 2020
    Assignee: Intel Corporation
    Inventors: David J. Zimmerman, Robert M. Ellis, Rajesh Sundaram
  • Publication number: 20200019227
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Publication number: 20200019348
    Abstract: Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 16, 2020
    Inventors: Rajesh Sundaram, Zion S. Kwok, Muthukumar Swaminathan
  • Patent number: 10534747
    Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram, Jawad B. Khan
  • Patent number: 10504591
    Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Rajesh Sundaram, David J. Zimmerman, Blaise Fanning
  • Publication number: 20190370112
    Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 5, 2019
    Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS
  • Publication number: 20190362764
    Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventors: Shekoufeh QAWAMI, Michael J. ALLEN, Rajesh SUNDARAM
  • Patent number: 10482566
    Abstract: Methods, apparatus, and machine-readable mediums are described for doing predictive content branch selection for rendering environments such as virtual reality systems. User data is aggregated from multiple users. Each user is classified based upon the user data. Personalization parameters are identified for each of the plurality of users. Content to be presented is determined and modified with a modification for a user based upon the personalization parameters for the user. The modified content is sent to the user.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh Poornachandran, Niveditha Sundaram, Ryan D. Saffores, Kalyan K. Kaipa, Gomathi Ramamurthy
  • Publication number: 20190332278
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Application
    Filed: May 31, 2019
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Publication number: 20190310911
    Abstract: Technologies for provisioning error-corrected data for use in in-memory compute operations include a memory that includes a memory media having multiple memory partitions and media access circuitry coupled to the memory media. The media access circuitry is to receive a request to perform an in-memory compute operation on data from the memory media. The request specifies a memory partition of the memory media in which the data is located. The media access circuitry reads the data from the memory partition. The media access circuitry performs error correction on the read data to produce error-corrected read data and stores the error-corrected read data in a temporary buffer for access by one or more in-memory compute operations, in addition to the requested in-memory compute operation.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 10, 2019
    Inventors: Rajesh Sundaram, Wei Wu, Chetan Chauhan, Srikanth Srinivasan, Shigeki Tomishima
  • Patent number: 10437307
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh Sundaram, William Low, Sowmiya Jayachandran
  • Publication number: 20190303237
    Abstract: Technologies for preserving error correction capability in compute-near-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 3, 2019
    Inventors: Chetan Chauhan, Wei Wu, Rajesh Sundaram, Shigeki Tomishima
  • Publication number: 20190272121
    Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram
  • Publication number: 20190272173
    Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.
    Type: Application
    Filed: May 22, 2019
    Publication date: September 5, 2019
    Inventors: Bruce Querbach, Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram
  • Publication number: 20190266219
    Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 29, 2019
    Inventors: Chetan Chauhan, Rajesh Sundaram, Richard Coulson, Bruce Querbach, Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan
  • Patent number: 10381055
    Abstract: A memory device performs DLL (delay locked loop) calibration in accordance with a DLL calibration mode configured for the memory device. A host controller can configure the calibration mode based on operating conditions for the memory device. The memory device includes an input/output (I/O) interface circuit and a delay locked loop (DLL) circuit coupled to control I/O timing of the I/O interface. A control circuit of the memory device selectively enables and disables DLL calibration in accordance with the DLL calibration mode. When selectively enabled, the DLL calibration is to operate at a time interval identified by the DLL calibration mode, and when selectively disabled, the DLL calibration is to cease or refrain from DLL calibration operations.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Shekoufeh Qawami, Michael J Allen, Rajesh Sundaram
  • Publication number: 20190227750
    Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Srikanth Srinivasan, Richard Coulson, Rajesh Sundaram, Bruce Querbach, Jawad B. Khan, Shigeki Tomishima, Sriram Vangal, Wei Wu, Chetan Chauhan
  • Publication number: 20190227981
    Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram, Jawad B. Khan
  • Publication number: 20190227871
    Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Inventors: Wei Wu, Rajesh Sundaram, Chetan Chauhan, Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan
  • Publication number: 20190228809
    Abstract: Technologies for providing high efficiency compute architecture on cross point memory for artificial intelligence operations include a memory that includes media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, including broadcasting matrix data associated with one partition of the memory media to multiple other partitions of the memory media. The media access circuitry is also to perform, with each of multiple compute logic units associated with different partitions of the memory media, a tensor operation on the matrix data and write, to the memory media, resultant data indicative of a result of the tensor operation.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Srikanth Srinivasan, Rajesh Sundaram, Jawad B. Khan, Shigeki Tomishima, Sriram Vangal, Chetan Chauhan