Patents by Inventor Rajesh

Rajesh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271289
    Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 8, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkateswar Kowkutla, Raghavendra Santhanagopal, Chunhua Hu, Anthony Frederick Seely, Nishanth Menon, Rajesh Kumar Vanga, Rejitha Nair, Siva Srinivas Kothamasu, Kazunobu Shin, Jason Peck, John Apostol
  • Patent number: 12273505
    Abstract: According to an example embodiment, a stereoscopic near-eye display (NED) assembly for a NED device including a pair of NED assemblies is provided, where an input image is subjected to a preprocessing procedure that applies image-area-position dependent preprocessing before providing it for viewing through a lens assembly that comprises a diffractive optical element (DOE) arranged to provide a phase delay that is different through a plurality of positions of its aperture. According to other example embodiments, an apparatus and a method for deriving the preprocessing procedure and the DOE are provided.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 8, 2025
    Assignee: TAMPERE UNIVERSITY FOUNDATION SR
    Inventors: Erdem Sahin, Ugur Akpinar, Atanas Gotchev, Rajesh Menon
  • Patent number: 12271703
    Abstract: Techniques are disclosed herein relating to using reinforcement learning to generate a dialogue policy. A computer system may perform an iterative training operation to train a deep Q-learning network (DQN) based on conversation logs from prior conversations. In various embodiments, the DQN may include an input layer to receive an input value indicative of a current state of a given conversation, one or more hidden layers, and an output layer that includes a set of nodes corresponding to available responses. During the iterative training operation, the disclosed techniques may analyze utterances from a conversation log and, based on the utterances, use the DQN to determine appropriate responses. Reward values may be determined based on the selected responses and, based on the reward values, the DQN may be updated. Once generated, the dialogue policy may be used by a chatbot system to guide conversations with users.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: April 8, 2025
    Assignee: PayPal, Inc.
    Inventor: Rajesh Virupaksha Munavalli
  • Patent number: 12271616
    Abstract: An embodiment of an integrated circuit comprises circuitry to share page tables associated with a page between a processor memory management unit (MMU) and an input/output memory management unit (IOMMU), store a page table entry in the memory associated with the page, and separately control access to the page from a processor and from a direct memory access (DMA) request based on one or more fields of the stored page table entry. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Utkarsh Y. Kakaiya, David Koufaty, Rajesh Sankaran, Vedvyas Shanbhogue
  • Patent number: 12272677
    Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: April 8, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar, Thomas Workman, Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Belgacem Haba, Gabriel Z. Guevara, Joy Watanabe
  • Publication number: 20250113627
    Abstract: An image sensor using quantum dots is formed that improves collection of photogenerated carrier using a conductive matrix, a semiconductive matrix, a matrix comprising conductive particles and quantum dots in a transparent non-conductive material, conductive structures, and/or porous conductive structures. Hybrid bonding of the image sensor to an image processor device is performed without use of an intervening adhesive to connect the image sensor to the image processor device.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Oliver Zhao
  • Publication number: 20250113646
    Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh
  • Publication number: 20250113700
    Abstract: Conductive features of a device including quantum dots of a first substrate are bonded to conductive features of a second substrate. A quantum dot layer is formed on the first substrate having conductive features in a dielectric layer. Hybrid bonding of the first substrate to the second substrate is performed without use of an intervening adhesive to connect the first conductive features and the second conductive features.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh
  • Publication number: 20250113641
    Abstract: A method of forming a stacked image sensor comprises providing a first substrate and a second substrate. The first substrate comprises a first matrix comprising first quantum dots, a first dielectric layer adjacent to the first matrix, and first bond pads disposed in the first dielectric layer. The second substrate comprises a second matrix comprising second quantum dots, a second dielectric layer adjacent to the second matrix, and second bond pads disposed in the second dielectric layer. The method includes hybrid bonding the first substrate to the second substrate without use of an intervening adhesive to form the stacked image sensor, where the hybrid bonding connects the first bond pads to the second bond pads.
    Type: Application
    Filed: September 25, 2024
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Belgacem Haba, Cyprian Emeka Uzoh, Oliver Zhao
  • Publication number: 20250108040
    Abstract: The present disclosure relates to the use of stimulators of soluble guanylate cyclase (sGC), pharmaceutically acceptable salts thereof and pharmaceutical formulations or dosage forms comprising them, alone or in combination with one or more additional agents, for the treatment of various CNS diseases, wherein an increase in sGC stimulation, or an increase in the concentration of nitric oxide (NO), or cyclic guanosine 3?,5?-monophosphate (cGMP) or both, or an upregulation of the NO pathway is desirable.
    Type: Application
    Filed: July 31, 2024
    Publication date: April 3, 2025
    Inventors: Joon Jung, Thomas Wai-Ho Lee, Rajesh R. Lyengar, Nicholas Robert Perl, Peter Germano, Maria D. Ribadeneira, Kim Tang
  • Publication number: 20250112123
    Abstract: Disclosed is a microelectronic structure including a first element and a through substrate via (TSV) structure. The first element includes a bulk portion having a front side and a back side opposite the front side. The TSV structure is disposed in an opening extending at least partially through the bulk portion from the front side to the back side. The TSV structure includes a conductive tip portion and a second conductive via portion. The second conductive via portion is disposed between the front side and the conductive tip portion. The conductive tip portion contains a different conductive material than the second conductive via portion.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 3, 2025
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh
  • Publication number: 20250112164
    Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
  • Publication number: 20250110768
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The memory may be configured to store one or more directories comprising access to multiple tenant profiles and one or more network access commands configured to provide access to one or more entitlements. Each tenant profile of the tenant profiles are associated with one or more services. The processor may be configured to receive a request to access at least one service. The request comprises an application function identifier (AFID). The tenant ID references a tenant profile of the tenant profiles. The department ID references multiple entitlements associated with the tenant profile. The API ID references a service associated with the entitlements. Further, the processor may be configured to determine multiple network access commands configured to enable access to the service in accordance with the entitlements and generate a report comprising the network access commands.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Inventors: Kazi Bashir, Julio Armenta, Rajesh Chilka, Mehdi Alasti, Siddhartha Chenumolu
  • Publication number: 20250112926
    Abstract: An apparatus comprises a memory and a processor communicatively coupled to one another. The memory may be configured to store one or more directories comprising access to multiple tenant profiles and one or more network access commands configured to provide access to one or more entitlements. Each tenant profile of the tenant profiles are associated with one or more services. The processor may be configured to receive a request to access at least one service. The request comprises an application function identifier (AFID) comprising a tenant ID that references a tenant profile of the tenant profiles, a department ID that references multiple entitlements associated with the tenant profile, and an API ID that references a service associated with the entitlements. Further, the processor may be configured to generate a report comprising multiple network access commands configured to enable access to the service in accordance with the entitlements.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Inventors: Kazi Bashir, Rajesh Chilka, Mehdi Alasti, Siddhartha Chenumolu
  • Patent number: 12262729
    Abstract: The present disclosure provides aerosol generating substrates and aerosol source members comprising aerosol generating substrates, as well as methods of manufacturing thereof. In an example implementation, an aerosol generating substrate may comprise a fibrous filler material, an aerosol forming material, and a plurality of heat conducting constituents, wherein the substrate is formed as a sheet, and wherein the heat conducting constituents are part of the sheet. The heat conducting constituents may be incorporated within the sheet, or may be formed on a surface of the sheet. In another example implementation, an aerosol source member may comprise a substrate portion formed of a collection of intermingled pieces cut from an aerosol substrate sheet. In addition, or alternatively, a substrate portion may be formed of a series of overlapping layers of an aerosol substrate sheet.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: April 1, 2025
    Assignee: RAI STRATEGIC HOLDINGS, INC.
    Inventors: Andries Sebastian, Stephen Benson Sears, Billy Tyrone Conner, Rajesh Sur, S. Keith Cole, Thaddeus Jackson, Timothy Frederick Thomas, Paul E. Braxton, Curtis Foster Doe, Vahid Hejazi, Kathryn Lynn Wilberding
  • Patent number: 12267882
    Abstract: Reporting potential impacts of sounding reference signal-switching (SRS-switching) to a base station may include determining that SRS-switching is to be performed by a UE. Based on determining that SRS-switching is to be performed, potential impacts to one or more of a plurality of radio access technologies (RATs) caused by performing SRS-switching while sharing radio frequency (RF) front-ends (RFFE) between at least a subset of the plurality of RATS may be processed. The potential impacts may comprise at least one of transmit-blanking (Tx-blanking) and receive-blanking (Rx-blanking) associated with one or more of the subset of RATs. A communication that indicates the potential impacts of SRS-switching may be encoded for transmission to a base station. The base station may also provide priority configurations for determining how to handle Tx-blanking, Rx-blanking, and SRS-skipping associated with SRS-switching.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: April 1, 2025
    Assignee: APPLE INC.
    Inventors: Pengkai Zhao, Dawei Zhang, Edmund J. Stocks, Fangli Xu, Haijing Hu, Haitong Sun, Jie Cui, Madhusudan Chaudhary, Rajesh Ambati, Thanigaivelu Elangovan, Wei Zeng, Wen Zhao, Yang Tang
  • Patent number: 12266640
    Abstract: Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: April 1, 2025
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Jeremy Alfred Theil, Belgacem Haba, Rajesh Katkar
  • Patent number: 12267389
    Abstract: Methods, apparatus, systems and articles of manufacture to dynamically control devices based on distributed data are disclosed. An example apparatus includes a comparator to compare a first measurement measured by a first peer device to a second measurement, the second measurement being measured locally by the apparatus; and an operation adjuster to, when the comparison satisfies a threshold, adjust a measurement protocol of the first peer device.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Rita Wouhaybi, Rajesh Poornachandran
  • Patent number: 12267252
    Abstract: Techniques are provided for a high availability solution (e.g., a network attached storage (NAS) solution) with address preservation during switchover. A first virtual machine is deployed into a first domain and a second virtual machine is deployed into a second domain of a computing environment. The first and second virtual machines are configured as a node pair for providing clients with access to data stored within an aggregate comprising one or more storage structures within shared storage of the computing environment. A load balancer is utilized to manage logical interfaces used by clients to access the virtual machines. During switchover, the load balancer preserves an IP address used to mount and access a data share of the aggregate used by a client.
    Type: Grant
    Filed: December 15, 2023
    Date of Patent: April 1, 2025
    Assignee: NetApp, Inc.
    Inventors: Christopher Busick, Rajesh Rajaraman, James Silva
  • Patent number: 12265631
    Abstract: A system and method to analyze security across digital environments is provided. The system includes a report generation module to generate reports stating vulnerabilities in a software delivery pipeline. A recommendation engine is configured to perform a comprehensive analysis of the reports, verifies by cross-referencing with a CVE database to provide a rationalized and comprehensive view of the vulnerabilities. Further, the recommendation engine is configured to conduct an impact analysis using a ML model to determine the consequence of fixing the vulnerabilities and generates a score matrix based on a predefined threshold limit. Recommendations are provided to resolve the vulnerabilities based on the score matrix generated and impact analysis. The system includes a vulnerability remediation module to utilize the threshold limit to initiate automated vulnerability remediation thereby ensuring a secure and reliable development process.
    Type: Grant
    Filed: November 8, 2024
    Date of Patent: April 1, 2025
    Inventors: Ramnish Singh, Gaurav Aggarwal, Anantha Balasubramanian, Balaji Ramakrishnan, Rajesh Kannan