Abstract: Disclosed herein is a method and apparatus for controlling surface characteristics by measuring capacitance of a process kit ring. The method includes interfacing a ring with a jig assembly for measuring capacitance in at least a first location of the ring. The ring has that includes a top surface, a bottom surface, and an inner surface opposite an outer surface. At least the bottom surface has an external coating placed thereon. The method further includes contacting a measuring device to the first location on the outer surface proximate the bottom surface. The measuring device contacts an opening in the external coating to the body. The measuring device contacts a first conductive member that is electrically coupled to the ring. A capacitance is measured on the measuring device. The capacitance across the top surface is measured.

Abstract: Methods of semiconductor processing may include performing a process on a semiconductor substrate. The semiconductor substrate may be seated on a substrate support positioned within a processing region of a semiconductor processing chamber. The methods may include flowing a first backside gas through the substrate support at a first flow rate. The methods may include removing the semiconductor substrate from the processing region of the semiconductor processing chamber. The methods may include performing a plasma cleaning operation within the processing region of the semiconductor processing chamber. The methods may include flowing a second backside gas through the substrate support at a second flow rate. At least a portion of the second backside gas may flow into the processing region through accesses in the substrate support.

Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.

Abstract: Embodiments of this disclosure describe a feedback loop that can be used to maintain a nearly constant sheath voltage and thus creating a mono-energetic IEDF at the surface of the substrate. The system described herein consequently enables a precise control over the shape of IEDF and the profile of the features formed in the surface of the substrate.

Abstract: Embodiments for processing a substrate in a pulsed plasma chamber are provided. A processing apparatus with two chambers, separated by a plate fluidly connecting the chambers, includes a continuous wave (CW) controller, a pulse controller, and a system controller. The CW controller sets the voltage and the frequency for a first radio frequency (RF) power source coupled to a top electrode. The pulse controller is operable to set voltage, frequency, ON-period duration, and OFF-period duration for a pulsed RF signal generated by a second RF power source coupled to the bottom electrode. The system controller is operable to regulate the flow of species between the chambers to assist in the negative-ion etching, to neutralize excessive positive charge on the wafer surface during afterglow in the OFF-period, and to assist in the re-striking of the bottom plasma during the ON-period.

Abstract: Methods of semiconductor processing may include performing a process on a semiconductor substrate. The semiconductor substrate may be seated on a substrate support positioned within a processing region of a semiconductor processing chamber. The methods may include flowing a first backside gas through the substrate support at a first flow rate. The methods may include removing the semiconductor substrate from the processing region of the semiconductor processing chamber. The methods may include performing a plasma cleaning operation within the processing region of the semiconductor processing chamber. The methods may include flowing a second backside gas through the substrate support at a second flow rate. At least a portion of the second backside gas may flow into the processing region through accesses in the substrate support.

Abstract: Disclosed herein is a method and apparatus for controlling surface characteristics by measuring capacitance of a process kit ring. The method includes interfacing a ring with a jig assembly for measuring capacitance in at least a first location of the ring. The ring has that includes a top surface, a bottom surface, and an inner surface opposite an outer surface. At least the bottom surface has an external coating placed thereon. The method further includes contacting a measuring device to the first location on the outer surface proximate the bottom surface. The measuring device contacts an opening in the external coating to the body. The measuring device contacts a first conductive member that is electrically coupled to the ring. A capacitance is measured on the measuring device. The capacitance across the top surface is measured.

Abstract: Embodiments herein provide plasma processing chambers and methods configured for fine-tuning and control over a plasma sheath formed during the plasma-assisted processing of a semiconductor substrate. Embodiments include a sheath tuning scheme, including plasma processing chambers and methods, which can be used to tailor one or more characteristics of a plasma sheath formed between a bulk plasma and a substrate surface. Generally, the sheath tuning scheme provides differently configured pulsed voltage (PV) waveforms to a plurality of bias electrodes embedded beneath the surface of a substrate support in an arrangement where each of the electrodes can be used to differentially bias a surface region of a substrate positioned on the support. The sheath tuning scheme disclosed herein can thus be used to adjust and/or control the directionality, and energy and angular distributions of ions that bombard a substrate surface during a plasma-assisted etch process.

Abstract: Embodiments herein provide plasma processing chambers and methods configured for fine-tuning and control over a plasma sheath formed during the plasma-assisted processing of a semiconductor substrate. Embodiments include a sheath tuning scheme, including plasma processing chambers and methods, which can be used to tailor one or more characteristics of a plasma sheath formed between a bulk plasma and a substrate surface. Generally, the sheath tuning scheme provides differently configured pulsed voltage (PV) waveforms to a plurality of bias electrodes embedded beneath the surface of a substrate support in an arrangement where each of the electrodes can be used to differentially bias a surface region of a substrate positioned on the support. The sheath tuning scheme disclosed herein can thus be used to adjust and/or control the directionality, and energy and angular distributions of ions that bombard a substrate surface during a plasma-assisted etch process.

Abstract: Embodiments herein provide plasma processing chambers and methods configured for fine-tuning and control over a plasma sheath formed during the plasma-assisted processing of a semiconductor substrate. Embodiments include a sheath tuning scheme, including plasma processing chambers and methods, which can be used to tailor one or more characteristics of a plasma sheath formed between a bulk plasma and a substrate surface. Generally, the sheath tuning scheme provides differently configured pulsed voltage (PV) waveforms to a plurality of bias electrodes embedded beneath the surface of a substrate support in an arrangement where each of the electrodes can be used to differentially bias a surface region of a substrate positioned on the support. The sheath tuning scheme disclosed herein can thus be used to adjust and/or control the directionality, and energy and angular distributions of ions that bombard a substrate surface during a plasma-assisted etch process.

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. One or more layers on a substrate electrostatically secured to an electrostatic chuck within a chamber of the etch reactor is etched using a first plasma, causing an etchant byproduct to be generated. A portion of the one or more layers are covered by a photoresist. After the etching is complete, a second plasma is provided into the chamber for a time period sufficient to trim the photoresist and remove a portion of the etchant byproduct. A second time period sufficient to electrostatically discharge the substrate using the second plasma is determined. Responsive to deactivating one or more chucking electrodes of the electrostatic chuck, the second plasma is provided into the chamber for the second time period and the substrate is removed from the chamber.

Abstract: A plasma processing system includes a plasma chamber having a substrate support, and a multi-zone gas injection upper electrode disposed opposite the substrate support. An inner plasma region is defined between the upper electrode and the substrate support. The multi-zone gas injection upper electrode has a plurality of concentric gas injection zones. A confinement structure, which surrounds the inner plasma region, has an upper horizontal wall that interfaces with the outer electrode of the upper electrode. The confinement structure has a lower horizontal wall that interfaces with the substrate support, and includes a perforated confinement ring and a vertical wall that extends from the upper horizontal wall to the lower horizontal wall. The lower surface of the upper horizontal wall, an inner surface of the vertical wall, and an upper surface of the lower horizontal wall define a boundary of an outer plasma region, which surrounds the inner plasma region.

Abstract: Embodiments of the disclosure provided herein include an apparatus and method for the plasma processing of a substrate in a processing chamber. More specifically, embodiments of this disclosure describe a biasing scheme that is configured to provide a radio frequency (RF) generated RF waveform from an RF generator to one or more electrodes within a processing chamber and a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. The plasma process(es) disclosed herein can be used to control the shape of an ion energy distribution function (IEDF) and the interaction of the plasma with a surface of a substrate during plasma processing.

Abstract: Embodiments of substrate supports are provided herein. In some embodiments, a substrate support for use in a substrate processing chamber includes a ceramic plate having a first side configured to support a substrate and a second side opposite the first side, wherein the ceramic plate includes an electrode embedded in the ceramic plate; a ceramic ring disposed about the ceramic plate and having a first side and a second side opposite the first side, wherein the ceramic ring includes a chucking electrode and a heating element embedded in the ceramic ring; and a cooling plate coupled to the second side of the ceramic plate and the second side of the ceramic ring, wherein the cooling plate includes a radially inner portion, a radially outer portion, and a thermal break disposed therebetween.

Abstract: Embodiments provided herein generally include plasma processing systems configured to preferentially clean desired surfaces of a substrate support assembly by manipulating one or more characteristics of an in-situ plasma and related methods. In one embodiment, a plasma processing method includes generating a plasma in a processing region defined by a chamber lid and a substrate support assembly, exposing an edge ring and a substrate supporting surface to the plasma, and establishing a pulsed voltage (PV) waveform at the edge control electrode.

Abstract: Embodiments provided herein include an apparatus and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defectivity in features formed on the surface of the substrate, improving plasma etch rate, and increasing selectivity of etching material to mask and/or etching material to stop layer. In some embodiments, the apparatus and methods enable processes that can be used to prevent or reduce the effect of trapped charges, disposed within features formed on a substrate, on the etch rate and defect formation.

Abstract: Embodiments provided herein include an apparatus and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to reducing defectivity in features formed on the surface of the substrate, improving plasma etch rate, and increasing selectivity of etching material to mask and/or etching material to stop layer. In some embodiments, the apparatus and methods enable processes that can be used to prevent or reduce the effect of trapped charges, disposed within features formed on a substrate, on the etch rate and defect formation.

Abstract: Embodiments provided herein generally include plasma processing systems configured to preferentially clean desired surfaces of a substrate support assembly by manipulating one or more characteristics of an in-situ plasma and related methods. In one embodiment, a plasma processing method includes generating a plasma in a processing region defined by a chamber lid and a substrate support assembly, exposing an edge ring and a substrate supporting surface to the plasma, and establishing a pulsed voltage (PV) waveform at the edge control electrode.

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming a desired material layer on a substrate between, during, prior to or after a patterning process. In one embodiment, a method for forming a material layer on a substrate includes pulsing a first gas precursor onto a surface of a substrate, attaching a first element from the first gas precursor onto the surface of the substrate, maintaining a substrate temperature less than about 110 degrees Celsius, pulsing a second gas precursor onto the surface of the substrate, and attaching a second element from the second gas precursor to the first element on the surface of the substrate.

Abstract: A method for removing etchant byproduct from an etch reactor and discharging a substrate from an electrostatic chuck of the etch reactor is provided. A substrate may be electrostatically secured to an electrostatic chuck within a chamber of an etch reactor. A first plasma may be provided into the chamber to etch the substrate, causing an etchant byproduct to be generated. After the etching is complete, a second plasma may be provided into the chamber, wherein the second plasma is an oxygen containing plasma. The etchant byproduct may be removed and the first substrate may be discharged using the second plasma. The first substrate may be removed from the chamber and a second substrate may be inserted into the chamber without first performing an in-situ cleaning between the removal of the first substrate and the insertion of the second substrate.