Abstract: An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.

Abstract: An apparatus is presented. The apparatus includes a first circuit configured to predict temperatures of a location for a plurality of time instances based on measured temperatures and a second circuit configured to schedule a thermal mitigation function based on the predicted temperatures. A method of operating an apparatus is presented. The method includes measuring temperatures on an integrated circuit, predicting temperatures of a location for a plurality of time instances based on the measured temperatures, and scheduling a thermal mitigation function based on the predicted temperatures. An apparatus is presented. The apparatus includes means for measuring temperatures on an integrated circuit, means for predicting temperatures of a location for a plurality of time instances based on measured temperatures, and means for scheduling a thermal mitigation function based on the predicted temperatures.

Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.

Abstract: A system includes a computer processor including N cores; and a plurality of device aging sensors, wherein each one of the plurality of device aging sensors is disposed within a respective core, the plurality of device aging sensors being configured to communicate core aging information with a core scheduler in the computer processor, wherein the core scheduler is configured to make a first set of M cores available to a thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a first time period in which the core aging information indicates that aging of the first set of M cores is below a threshold, and wherein the core scheduler is configured to make a second set of M cores available to the thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a second time period.

Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.

Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.

Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

Abstract: An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.

Abstract: An apparatus is provided. The apparatus includes a plurality of counters configured to count electrical activity switching events of cores, a first circuit configured to predict a temperature at a location based on counts of at least one of the plurality of counters, and a second circuit configured to schedule a thermal mitigation function based on the predicted temperature. A method for scheduling thermal mitigation functions is provided. The method includes counting electrical activity switching events, predicting a temperature at a location based on the counting of the electrical activity switching events, and scheduling a thermal mitigation function based on the predicted temperature. Another apparatus is provided. The apparatus includes means for counting electrical activity switching events, means for predicting a temperature at a location based on a count of the electrical activity switching events, and means for scheduling a thermal mitigation function based on the predicted temperature.

Abstract: An apparatus is presented. The apparatus includes a first circuit configured to predict temperatures of a location for a plurality of time instances based on measured temperatures and a second circuit configured to schedule a thermal mitigation function based on the predicted temperatures. A method of operating an apparatus is presented. The method includes measuring temperatures on an integrated circuit, predicting temperatures of a location for a plurality of time instances based on the measured temperatures, and scheduling a thermal mitigation function based on the predicted temperatures. An apparatus is presented. The apparatus includes means for measuring temperatures on an integrated circuit, means for predicting temperatures of a location for a plurality of time instances based on measured temperatures, and means for scheduling a thermal mitigation function based on the predicted temperatures.

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.

Abstract: Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

Abstract: A thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain static and/or transient thermal simulations of the chips based on thermal models and boundary conditions. The thermal simulations are performed in accordance with one or more grids, with boundaries and/or resolutions being determined by adaptive and/or hierarchical multi-dimensional techniques. The adaptive grid techniques include material-boundary, rate-of-change, and convergence-information heuristics. For example, a finer grid is used in a region having higher temperature gradients compared to a region having lower temperature gradients. The hierarchical grid techniques are based on critical, intermediate, and boundary regions specified manually or automatically, each region having a respective grid resolution.

Abstract: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

Abstract: Transient thermal simulation of semiconductor chips uses region-wise variable spatial grids and variable temporal intervals, enabling spatio-temporal thermal analysis of semiconductor chips. Temperature rates of change across a die and/or package of an integrated circuit are computed and tracked versus time. Critical time interval(s) for temperature evaluation are determined. Temperatures of elements, components, devices, and interconnects are updated based on a 3D full chip temperature analysis. Respective power dissipations are updated, as a function of the temperatures, with an automated interface to one or more circuit simulation tools. Subsequently new temperatures are determined as a function of the power dissipations. User definable control and observation parameters enable flexible and efficient transient thermal analysis. The parameters relate to power sources, monitoring, reporting, error tolerances, and output snapshots.

Abstract: In a first variation, a thermally aware design automation suite integrates system-level thermal awareness into design of semiconductor chips, performing fine-grain thermal simulations of the chips based on thermal models and boundary conditions. The suite uses results of the simulations to modify thermally significant structures to achieve desired thermal variations across a chip, meet design assertions on selected portions of the chip, and verify overall performance and reliability of the chip over designated operating ranges and manufacturing variations. In a second variation, a discretization approach models chip temperature distributions using heuristics to adaptively grid space in three dimensions. Adaptive and locally variable grid spacing techniques are used to efficiently and accurately converge for steady state and/or transient temperature solutions.

Abstract: A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than assumed or estimated) temperature of a semiconductor device and/or an interconnects in the semiconductor ship design. This input is then used to assess at least one temperature-dependent performance parameter of the semiconductor chip design.

Abstract: Thermally aware design improvement enables increasing performance, reliability, and other related metrics by performing a multi-dimensional thermal analysis of a design of an electronic component in an assumed operating environment. Results of the analysis are then used to drive optimizations and repairs to the design. The performance metrics include maximum and minimum operating frequency, leakage current, power consumption, temperature gradient, absolute temperature, and other related parameters. The reliability metrics include Mean Time Between Failure (MTBF), required burn-in time, and other related parameters. In a related aspect, thermally aware design improvement enables performance driven electronic component design optimization and repair, including improving aspects of the physical design of an included semiconductor die. Improvements include modifying design details such as placement and routing of individual elements of the die.