Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.

Abstract: A method and apparatus for full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal analysis of a semiconductor chip design comprises receiving at least one input relating to a semiconductor chip design to be analyzed. The input is then processed to produce a three-dimensional thermal model of the semiconductor chip design. In another embodiment, thermal analysis of the semiconductor chip design is performed by calculating power dissipated by transistors and interconnects included in the semiconductor chip design and distributing power dissipated by the interconnects.

Abstract: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

Abstract: A method and apparatus for retrofitting semiconductor chip performance analysis tools with full-chip thermal analysis capabilities is provided. One embodiment of a novel method for performing performance analysis of a semiconductor chip design includes receiving at least one input calculated in accordance with an actual (e.g., purposefully calculated rather than assumed or estimated) temperature of a semiconductor device and/or an interconnects in the semiconductor ship design. This input is then used to assess at least one temperature-dependent performance parameter of the semiconductor chip design.

Abstract: A method and apparatus for thermal testing of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and positioning temperature sensors within a corresponding semiconductor chip in accordance with the calculated full-chip temperatures (e.g., in the regions of steep thermal gradients). Thus, temperature sensors are strategically placed in the regions where they are most likely to be needed, according to calculated temperatures, rather than randomly positioned throughout a test chip.

Abstract: A method for formal automated signal analysis upon elements of a design of a electronic circuit. The method includes (1) categorizing said elements into one of a plurality of types; (2) initiating a technique for characterizing the immunity of said given element to electrical signal effects, and (3) determining, based on said characterizing, whether a signal integrity violation will occur as a result of said given element, and if a violation will occur, how said violation could be repaired.

Abstract: Techniques for analyzing circuit designs based on assertions. An assertion is associated with a circuit structure from the circuit design. The assertion specifies a context of the circuit design in which the circuit structure is to be analyzed, an attribute associated with the circuit structure, and a constraint associated with the attribute. The present invention analyzes the circuit design based on assertions and checks to identify one or more instances of the circuit structure in the circuit design which do not satisfy the constraint specified in the assertion. An assertion may also indicate an action to be performed if the circuit structure does not satisfy the constraint specified in the assertion.