Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Abstract: An embodiment intercepts a notification including a portion of natural language text and a Uniform Resource Locator (URL). An embodiment identifies, using a natural language understanding model, a topic of the notification. An embodiment tags, using a content summarization model, a content located at the URL, the tagging comprising assigning a set of content tags to the content, the set of content tags comprising a predefined tag representing the content. An embodiment calculates a relevancy score scoring a comparison between the set of content tags and a set of user tags, the set of user tags comprising a predefined tag representing a profile of an intended recipient of the notification. An embodiment generates, responsive to the relevancy score being above a threshold, using the topic and the set of content tags, a customized notification, the customized notification replacing the notification.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) cell array and a first assist circuit and a differently configured second assist circuit. The first assist circuit is configured to apply a voltage boost to an access line utilized to access the SRAM cell array, and the second assist circuit is configured to apply a voltage boost to a voltage supply rail of the SRAM cell array. A common boost capacitor is coupled to selectively and concurrently provide a voltage boost to both the access line and the power rail via the first and second assist circuits, respectively.

Abstract: An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) array including a conductive line and an assist circuit having a boost capacitor coupled to boost a voltage on the conductive line. The boost capacitor includes first and second plates. The integrated circuit further includes a sense circuit having an input coupled to one of the first and second plates of the boost capacitor and an output and a sample circuit coupled to the output of the sense circuit. The sample circuit is configured to detect a short circuit in the boost capacitor based on a state change at the output of the sense circuit.

Abstract: An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.

Abstract: An embodiment for maintaining service level objectives in container orchestration platforms using constraint propagation. The embodiment may receive a set of service level objectives associated with deployment of an application. The embodiment may determine a series of resource dependencies corresponding to the received set of service level objectives for the application. The embodiment may generate a first set of constraints corresponding to service requirements for the received set of service level objectives. The embodiment may generate a second set of constraints corresponding to relationships within a target cluster between the target cluster resources and the series of resource dependencies. The embodiment may detect violations of the first set of constraints, and then determine one or more remediation measures to restore the received set of service level objectives based on the second set of constraints to output the one or more remediation measures to an end user.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for providing a virtual power supply through a wafer backside. In a non-limiting embodiment of the invention, a front end of line structure having a gate is formed and a back end of line structure is formed on a first surface of the front end of line structure. A backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

Abstract: A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Abstract: An apparatus includes a current-mode multiply-accumulate (MAC) core with a plurality of parallel current carrying paths. Each path is configured to carry a unit current based on a state of an input variable, a weight, and a configuration vector. The plurality of current carrying paths are arranged in groups, and each group has a summation line. Also included are a plurality of current mode interfaces. Each current mode interface of the plurality of current mode interfaces is coupled to a corresponding summation line of the plurality of summation lines. A plurality of current mode comparators are coupled to the plurality of current mode interfaces and configured to compare current on the corresponding one of the plurality of summation lines to a plurality of corresponding reference currents.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor chip having a frontside and a backside; a first metal level at the backside of the semiconductor chip; a second metal level above the first metal level; a plurality of damascene vias extending from the second metal level towards the first metal level; and a plurality of subtractive vias extending from the first metal level towards the second metal level, wherein the plurality of damascene vias and the plurality of subtractive vias are staggered to form an interdigitated comb-comb structure. A method of forming the semiconductor structure is also provided.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for providing a virtual power supply through a wafer backside. In a non-limiting embodiment of the invention, a front end of line structure having a gate is formed and a back end of line structure is formed on a first surface of the front end of line structure. A backside power delivery network is formed on a second surface of the front end of line structure opposite the first surface. Source and drain regions on a first side of the gate are connected to the backside power delivery network and source and drain regions on a second side of the gate are connected to the back end of line structure.

Abstract: A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

Abstract: A wireless power system includes a phase locked loop (PLL) providing an input signal tuned in frequency, a plurality of dividers coupled to the PLL to divide the frequency of the input signal, a plurality of phase interpolators electrically connected to the plurality of dividers to generate multiple phases based on the input signal, and a plurality of drivers electrically connected to the plurality of phase interpolators to direct a plurality of output signals each having a different frequency to a plurality of sensor clusters, each sensor cluster operating at a different frequency.

Abstract: An apparatus includes a memory array. The array in turn includes a plurality of word lines, a plurality of bit line pairs intersecting the plurality of word lines at a plurality of cell locations, and a plurality of memory cells, coupled to the plurality of word lines and the plurality of bit line pairs, and located at the plurality of cell locations. A plurality of word line drivers are coupled to the plurality of word lines, a dynamic voltage boost is coupled to the memory array, and a controller is coupled to the plurality of word line drivers and the dynamic voltage boost. The controller is configured to cause the dynamic voltage boost to boost the cells during a multiply accumulate operation.

Abstract: Mechanisms are provided for optimizing remuneration for computing services. Computing services are registered which stores registration data comprising remuneration associations between computing services and consumers. A hierarchical computer model is generated based on the registration data, where the model represents dependencies between consumers and providers of computing services. For a service request from a consumer, each transaction with each computing service in a service invocation chain associated with the service request is identified and a cost of each transaction is calculated. The calculated cost of the service invocation chain is optimized based on applying an optimization algorithm to a cost function applied to a selected portion of the hierarchical computer model corresponding to the service invocation chain.

Abstract: A method, programming product, and/or system is disclosed for accounting for random (idiosyncratic) factors (Z) in a loss function influenced by both systemic factors (Y) and random factors (Z) and includes: computing an initial center of gravity (initial COG) of a loss function; and adjusting the initial COG of the loss function toward an Origin to a New COG to account for the random factors (Z). The New COG is determined in an approach and includes: performing a Monte Carlo sampling around an Origin to identify a Max loss at the Origin; performing a Monte Carlo sampling around the Initial COG to identify a Max loss at the Initial COG; and computing a distance to the New COG from the Initial COG using geometric ratios. In a further aspect, an importance sampling is performed about the New COG.

Abstract: Transmitters and methods of transmitting a polar-modulated signal include a driver to output a polar-modulated signal according to a phase-modulation signal and an amplitude-modulation signal. A voltage regulator is connected to the driver, with the amplitude-modulation signal controlling an input of the voltage regulator and with the amplitude-modulation signal further being combined with an output of the voltage regulator to control an amplitude of the output of the driver to compensate for bandwidth cutoff noise in the voltage regulator.

Abstract: A singled ended current sense amplifier circuit including an input stage having a bitline node, a sense node and a feedback circuit comprising a feedback inverter configured to provide an amplified voltage from the bitline node. The feedback inverter may include first and second NMOS transistors serially connected to a feedback node and first and second PMOS transistors serially connected to the feedback node. The feedback circuit may include a third NMOS transistor having a gate terminal connected to the feedback node and a drain terminal connected to the sense node. The input stage may include a third PMOS transistor operating as a current source to generate a sense current which flows in a current sensing path between the sense node and the bitline node. The input stage may act as a regulator to keep the voltage at the bitline node constant.

Abstract: An apparatus includes a plurality of signal processing stages configured to convert a digital baseband signal into an analog radio frequency signal for transmission. The signal processing stages are configured to be operatively coupled to a positive supply voltage and a negative supply voltage. At least one signal processing stage of the plurality of signal processing stages is configured to generate an analog voltage signal which comprises a voltage level that is outside of a voltage range defined by the positive supply voltage and the negative supply voltage.

Abstract: A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.