Patents by Inventor Rajiv Joshi

Rajiv Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11315613
    Abstract: Systems and methods for operating a digital-to-analog converter (DAC) are described. In an example, a device can receive a digital input. The device can generate a clock signal having frequency in radio frequency (RF) range. The device can combine the digital input with the clock signal to generate a first voltage signal. The device can convert the first voltage signal into a second voltage signal having at least two phases. The device can convert the second voltage signal into a current signal. The device can distribute the current signal to at least one current mode DAC.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 26, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11309479
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11276912
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11182690
    Abstract: A qubit controller includes an in-phase path and a quadrature path. A first combiner is configured to combine an output of the in-phase path with an output of the quadrature path to create a single sideband. There is a splitter configured to divide the single sideband into N portions, provide a first portion of the N portions to a qubit corresponding to the qubit controller, and provide each of the remaining N?1 portions to adjacent qubit controllers of a qubit cluster that includes the qubit corresponding to the qubit controller. A second combiner is configured to combine the first portion and N feedback signals received from the adjacent qubit controllers of the qubit cluster.
    Type: Grant
    Filed: May 2, 2020
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 11176486
    Abstract: Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include generating a user profile specifying a plurality of attribute values for a plurality of principle attributes, by processing a corpus of electronic documents using a first trained machine learning model. In an embodiment, the method further comprises generating a provider profile specifying a plurality of attribute values for the plurality of principle attributes, for each of a plurality of providers, by processing a respective corpus of electronic documents associated with each respective provider using a second trained machine learning model. A plurality of match coefficients based on comparing the user profile and the plurality of provider profiles are determined. Finally, one or more online interactions between the user and the target provider are influenced based on the determined match coefficients.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Avijit Chatterjee, Rajiv Joshi, John J. Thomas
  • Publication number: 20210342121
    Abstract: An improved electronic mixed mode multiplier and accumulate circuit for artificial intelligence and computing system applications that perform vector-vector, vector-matrix and other multiply-accumulate computations. The circuit is provided is a high resolution, high linearity, low area, low power multiply—accumulate (MAC) unit to interface with a memory device for storing computation output results. The MAC unit uses a less number of current carrying elements resulting in much lower integrated circuit area, and provides a tight matching between the current elements thus preserving inherent linearity requirements due to current mode operation. Further the MAC performs current scaling using switches and current division where the current switches occupy minimum size transistors requiring a small area to implement that renders it compatible with MRAM such as a magnetic tunnel junction device.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 4, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Publication number: 20210342726
    Abstract: A quantum write controller includes an in-phase path that includes a first digital to analog converter (DAC) configured to receive an in-phase signal at a first frequency, a first mixer configured to create a third in phase frequency, a first combiner configured to combine an output of the first mixer with an output of a third mixer, and a second mixer configured to mix an output of the first combiner with a fourth in phase frequency. There is a quadrature path that includes a second DAC configured to receive a quadrature phase signal at the first frequency, a third mixer configured to create a third quadrature frequency, a second combiner configured to combine the output of the third mixer with the output of the first mixer, and a fourth mixer configured to mix an output of the second combiner with a fourth quadrature frequency.
    Type: Application
    Filed: May 2, 2020
    Publication date: November 4, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Publication number: 20210341979
    Abstract: A quantum processing system includes a first set of control electronics operating at a first temperature. A second set of control electronics is communicatively coupled to the first set of control electronics and operating at a second controlled temperature that is lower than the first temperature. The second set of control electronics includes one or more circuits configured to perform a write and a read operation to one or more qubits. There is a qubit array that includes the one or more qubits and operating at a third controlled temperature that is lower than the second temperature. The qubit array is controlled by the second set of control electronics.
    Type: Application
    Filed: May 2, 2020
    Publication date: November 4, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Publication number: 20210342727
    Abstract: A qubit controller includes an in-phase path and a quadrature path. A first combiner is configured to combine an output of the in-phase path with an output of the quadrature path to create a single sideband. There is a splitter configured to divide the single sideband into N portions, provide a first portion of the N portions to a qubit corresponding to the qubit controller, and provide each of the remaining N?1 portions to adjacent qubit controllers of a qubit cluster that includes the qubit corresponding to the qubit controller. A second combiner is configured to combine the first portion and N feedback signals received from the adjacent qubit controllers of the qubit cluster.
    Type: Application
    Filed: May 2, 2020
    Publication date: November 4, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 11158297
    Abstract: A timbre creation method, system, and computer program product include performing a timbre analysis of a sound from an input source to generate a digital fingerprint of the sound, performing deep learning to create a patch that matches the digital fingerprint, and generating a second patch for a synthesizer which reproduces a timbre that complements the digital fingerprint based on the patch.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark Sobierajski, Hubertus Franke, Felipe Ferraz Telles, Rajiv Joshi
  • Patent number: 11157980
    Abstract: Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include receiving, from a first user of a plurality of users, a first set of electronic documents, where each electronic document in the first set of electronic documents corresponds to a respective user in the plurality of users. The methods also include identifying a plurality of user profiles, where each of the plurality of user profiles was generated by processing a corpus of electronic documents associated with each respective user using a first trained machine learning model. The methods include determining a plurality of match coefficients, based on comparing a plurality of user profiles associated with each respective user in the plurality of users, filtering the first set of electronic documents based on the plurality of match coefficients, and providing the filtered first set of electronic documents to the first user.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Avijit Chatterjee, Rajiv Joshi, John J. Thomas
  • Publication number: 20210326112
    Abstract: System and methods for implementing a multiply and accumulate (MAC) operation are described. In an example, a device can multiply an input digital signal with an input current to generate a current signal. The device can further divide the current signal into a plurality of currents. The device can further sample the plurality of currents sequentially using the same clock frequency. The device can further combine the plurality of sampled currents to generate an output current signal.
    Type: Application
    Filed: April 21, 2020
    Publication date: October 21, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 11152890
    Abstract: A voltage controlled oscillator (VCO) circuit employing digital amplitude control of the output oscillating signal and method of operation. The digital control is provided by an analog to digital converter (ADC) element that is shared among many other operating blocks in a system. In a configuration, the oscillator current is obtained by implementing transistors in a linear region and controlling them digitally. The optimum amplitude detection is performed by measuring the DC voltage at the common mode nodes in the oscillator, and is realized using reduced time compared to an extensive frequency measurement over a long time window. The digital control is implemented using an on-chip regulator, and employs digital controls for adjusting the current consumption which leads to low on-chip area overhead, low cost, and a scalable implementation. In an implementation, a one-time code can be obtained for optimum phase noise operation when providing the digital amplitude control.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Bruce B. Doris
  • Publication number: 20210311108
    Abstract: Systems and methods for monitoring current anomaly are described. In an example, a device can measure first current flowing along a first liner between an instrument to an equipment. The device can measure second current flowing along a second line between the equipment to the instrument. The device can compare the measurements of the first current and the second current. The device can identify a presence of current anomaly based on the comparison of the measurements of the first and second currents. The device can, in response to the presence of the current anomaly, disconnect the instrument from the equipment.
    Type: Application
    Filed: April 3, 2020
    Publication date: October 7, 2021
    Inventors: Felipe Ferraz Telles, Mark Sobierajski, Hubertus Franke, Rajiv Joshi
  • Patent number: 11120864
    Abstract: A structure of a memory device is described. The structure can include an array of memory cells. A memory cell can include at least one metal-oxide-semiconductor (MOS) element, where a source terminal of the at least one MOS element is connected to a drain terminal of the MOS element. The source terminal being connected to the drain terminal can cause the at least one MOS element to exhibit capacitive behavior for storing electrical energy. A first transistor can be connected to the at least one MOS element, where an activation of the first transistor can facilitate a write operation to the memory cell. A second transistor can be connected to the at least one MOS element, where an activation of the second transistor can facilitate a read operation from the memory cell.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11121675
    Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11114991
    Abstract: An analog front-end (AFE) circuit for conditioning a sensor signal is disclosed. The AFE circuit includes a first stage configured to amplify and filter the sensor signal. The first stage comprises a biquadratic filter comprising a first plurality of DC-coupled transconductance amplifiers. The AFE further includes a second stage configured to further amplify and filter the amplified sensor signal, and to compensate a direct current (DC) offset of the first stage. The second stage comprises a second plurality of AC-coupled transconductance amplifiers. Each transconductance amplifier of the first plurality and of the second plurality has a programmable transconductance and comprises a plurality of subthreshold-biased transistors.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Publication number: 20210272611
    Abstract: Systems and methods for operating a digital-to-analog converter (DAC) are described. In an example, a device can receive a digital input. The device can generate a clock signal having frequency in radio frequency (RF) range. The device can combine the digital input with the clock signal to generate a first voltage signal. The device can convert the first voltage signal into a second voltage signal having at least two phases. The device can convert the second voltage signal into a current signal. The device can distribute the current signal to at least one current mode DAC.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210217396
    Abstract: A timbre creation method, system, and computer program product include performing a timbre analysis of a sound from an input source to generate a digital fingerprint of the sound, performing deep learning to create a patch that matches the digital fingerprint, and generating a second patch for a synthesizer which reproduces a timbre that complements the digital fingerprint based on the patch.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: Mark Sobierajski, Hubertus Franke, Felipe Ferraz Telles, Rajiv Joshi
  • Publication number: 20210208848
    Abstract: Systems and methods to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a first current mode digital-to-analog converter (DAC) configured to multiply an input signal with a first current having a first amplitude to generate a first signal. The device can further include a second current mode DAC configured to multiply the input signal with a second current having a second amplitude to generate a second signal. The second amplitude can be less than the first amplitude. The device can further include a mixer configured to multiply the second signal with a clock signal to generate a third signal. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi