Patents by Inventor Rajiv Vasant Joshi
Rajiv Vasant Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10139446Abstract: A method and a system including a processor performing a failure region exploration through uniform sampling of plurality of variables related to a circuit, the processor shifting probability distributions to explore failure probability, the processor estimating the failure probability and standard deviation by determining mean and standard deviation of failure probability of a circuit, the processor terminating sampling when a confidence interval bounds converge, and a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.Type: GrantFiled: August 28, 2015Date of Patent: November 27, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajiv Vasant Joshi, Emrah Acar
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Publication number: 20170059649Abstract: A method and a system including a processor performing a failure region exploration through uniform sampling of plurality of variables related to a circuit, the processor shifting probability distributions to explore failure probability, the processor estimating the failure probability and standard deviation by determining mean and standard deviation of failure probability of a circuit, the processor terminating sampling when a confidence interval bounds converge, and a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.Type: ApplicationFiled: August 28, 2015Publication date: March 2, 2017Inventors: Rajiv Vasant Joshi, Emrah Acar
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Patent number: 9256704Abstract: A method (and program) for conducting numerical analysis, includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, if a component of the plurality of components is defined in the table, acquiring a result for the condition to be analyzed based on the table information, and conducting the analysis of the system using the result based on the table information for the component.Type: GrantFiled: January 31, 2014Date of Patent: February 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Emrah Acar, Rajiv Vasant Joshi, Tong Li
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Publication number: 20150220671Abstract: A method (and program) for conducting numerical analysis, includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, if a component of the plurality of components is defined in the table, acquiring a result for the condition to be analyzed based on the table information, and conducting the analysis of the system using the result based on the table information for the component.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Applicant: International Business Machines CorporationInventors: Emrah Acar, Rajiv Vasant Joshi, Tong Li
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Patent number: 8880382Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.Type: GrantFiled: January 18, 2012Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E Rosenbluth, Rama N. Singh, Kehan Tian
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Patent number: 8682634Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.Type: GrantFiled: September 13, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E Rosenbluth, Rama N. Singh, Kehan Tian
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Publication number: 20130185046Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.Type: ApplicationFiled: September 13, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: Saeed Bagheri, Fook-Luen Heng, Rajiv Vasant Joshi, Kafai Lai, David Osmond Melville, Saibal Mukhopadhyay, Alan E. Rosenbluth, Rama N. Singh, Kehan Tian
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Publication number: 20130185045Abstract: Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.Type: ApplicationFiled: January 18, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: Saeed BAGHERI, Fook-Luen HENG, Rajiv Vasant JOSHI, Kafai LAI, David Osmond MELVILLE, Saibal MUKHOPADHYAY, Alan E. ROSENBLUTH, Rama N. SINGH, Kehan TIAN
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Patent number: 7911263Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.Type: GrantFiled: June 30, 2009Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Jong-Ru Guo, Louis Lu-Chen Hsu, Rajiv Vasant Joshi, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20100327958Abstract: A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Inventors: Jong-Ru Guo, Louis Lu-Chen Hsu, Rajiv Vasant Joshi, Ping-Chuan Wang, Zhijian Yang
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Patent number: 7232745Abstract: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.Type: GrantFiled: February 24, 2005Date of Patent: June 19, 2007Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Louis C. Hsu, Rajiv Vasant Joshi
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Patent number: 7158604Abstract: A system and method for the superimposition of differential signals on binary signals in a memory system. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.Type: GrantFiled: May 28, 1998Date of Patent: January 2, 2007Assignee: International Business Machines Corp.Inventors: Philip George Emma, Rajiv Vasant Joshi, William Robert Reohr
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Patent number: 6943105Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.Type: GrantFiled: February 23, 2004Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventor: Rajiv Vasant Joshi
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Publication number: 20040180541Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.Type: ApplicationFiled: February 23, 2004Publication date: September 16, 2004Applicant: International Business Machines CorporationInventor: Rajiv Vasant Joshi
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Patent number: 6444565Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.Type: GrantFiled: June 29, 2001Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Christopher Adam Feild, Roy Charles Iggulden, Rajiv Vasant Joshi, Edward William Kiewra
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Patent number: 6433436Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.Type: GrantFiled: May 26, 1999Date of Patent: August 13, 2002Assignee: International Business Machines CorporationInventors: Christopher Adam Feild, Roy Charles Iggulden, Rajiv Vasant Joshi, Edward William Kiewra
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Publication number: 20020096768Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.Type: ApplicationFiled: January 18, 2002Publication date: July 25, 2002Applicant: International Business Machines CorporationInventor: Rajiv Vasant Joshi
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Patent number: 6335569Abstract: A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal.Type: GrantFiled: July 9, 1998Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventor: Rajiv Vasant Joshi
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Patent number: 6285082Abstract: A soft metal conductor for use in a semiconductor device that has an upper-most layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing step.Type: GrantFiled: January 3, 1995Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Rajiv Vasant Joshi, Manu Jamnadas Tejwani
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Patent number: 6279144Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. A memory array cell comprises a pair of cross-coupled inverters forming a first latch for storing data. The first latch has an output connected to a read bit line. True and complement write word and bit line input to the first latch. A first set of pass gates connects between the true and complement write word and bit line inputs via gates and the input of said first latch. The first set of pass gates is responsive to a first clock via a second pass gate. A pair of cross-coupled inverters forms a second latch of a Level Sensitive Scan Design (LSSD).Type: GrantFiled: August 19, 1999Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Walter Harvey Henkels, Wei Hwang, Rajiv Vasant Joshi, Albert Thomas Williams