Abstract: Self-reset and write control circuits for high performance asynchronous multiport register files are disclosed. The high speed write operation is achieved by the combination of static data input and dynamic data control circuits. The write timing signal generation, true and complement address buffer, decoder and wordline drivers, and write enable circuits employ the advantages of a fully custom designed methodology with self-resetting complementary metal oxide semiconductor (SRCMOS) circuit techniques. Individual write enable pulses applied to respective input ports of a multiport register cell are effective to establish a priority among those input ports. In this design, the priority of the B-write-port over the A-write-port is established when both write ports address the same register. The present invention provides an effective input isolation/decoupling circuit technique which allows the input pulse widths to vary over a wide range.

Abstract: A semiconductor chip structure includes a substrate, at least one thermal conductor embedded within the semiconductor chip structure, the thermal conductor providing electrical insulation and a plurality of devices formed within the structure adjacent to the at least one thermal conductor such that during operation heat produced in the devices is transferred into and through the at least one thermal conductor to reduce an operating temperature of the devices. This structure is particularly useful in silicon-on insulator devices. A method of forming embedded thermal conductors in a semiconductor chip includes the steps of providing a substrate having an oxide layer formed thereon, etching trenches into the oxide layer, depositing diamond to fill the trenches to form thermal conductors contacting the substrate and forming devices and contacts adjacent to the thermal conductors for providing heat flow paths to reduce an operating temperature of the devices.

Abstract: A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Abstract: A soft metal conductor for use in a semiconductor device that has an upper-most layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing step.

Abstract: A system and method for the superimposition of differential signals on binary signals. The technique can be performed on busses, and in many kinds of storage media. It can be accomplished in many ways depending on the noise that is to be tolerated, and depending on the sophistication of the encoding means.

Abstract: A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.

Abstract: A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

Abstract: A semiconductor chip structure includes a substrate, at least one thermal conductor embedded within the semiconductor chip structure, the thermal conductor providing electrical insulation and a plurality of devices formed within the structure adjacent to the at least one thermal conductor such that during operation heat produced in the devices is transferred into and through the at least one thermal conductor to reduce an operating temperature of the devices. This structure is particularly useful in silicon-on insulator devices. A method of forming embedded thermal conductors in a semiconductor chip includes the steps of providing a substrate having an oxide layer formed thereon, etching trenches into the oxide layer, depositing diamond to fill the trenches to form thermal conductors contacting the substrate and forming devices and contacts adjacent to the thermal conductors for providing heat flow paths to reduce an operating temperature of the devices.

Abstract: Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level.

Abstract: The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.

Abstract: A quasi-synchronous DRAM circuit uses a plurality of asynchronous DRAM macros organized in memory banks. An interface conversion circuit receives external synchronous control signals and generates internal control signals for each of the plurality of asynchronous DRAM macros. A data buffer circuit is connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus. The interface conversion circuit controls the data buffer to provide synchronous burst of data through frequency conversion.

Abstract: A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.

Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6, can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

Abstract: A computer-implemented method for a system having a database and a plurality of application software interfaces, the method including steps of reading a control type from a plurality of control types stored in the database, selecting an application software interface having a pointer based on the control type, defining an identification code for the control type, storing the pointer and the identification code and linking a first node to a second, subsequent node of control types and creating a linked list of the plurality of control types.

Abstract: An damascene x-ray mask comprises an oxide membrane layer having trenches formed therein defining an x-ray mask pattern. The trenches are filled with collimated, sputtered tungsten sputtered in a relatively high pressure environment. The result is a dense, low stress tungsten film completely filling the trenches. Damascene refers to the process by which the mask is formed. The mask is formed on a silicon substrate and then the substrate is etched away from the bottom side leaving substantially just the oxide layer and the collimated tungsten. The oxide layer is transparent to x-rays and the collimated tungsten layer is opaque to x-rays.

Abstract: A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.