Patents by Inventor Rajni J. Aggarwal
Rajni J. Aggarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150187759Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: ApplicationFiled: March 12, 2015Publication date: July 2, 2015Inventors: Rajni J. AGGARWAL, Jau-Yuann YANG
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Publication number: 20150187655Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.Type: ApplicationFiled: December 8, 2014Publication date: July 2, 2015Inventors: Ashesh PARIKH, Chi-Chien HO, Thomas John SMELKO, Rajni J. AGGARWAL
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Patent number: 9006838Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: GrantFiled: October 10, 2013Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Rajni J. Aggarwal, Jau-Yuann Yang
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Publication number: 20140370621Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.Type: ApplicationFiled: August 28, 2014Publication date: December 18, 2014Inventors: Rajni J. Aggarwal, Scott R. Summerfelt, Gul B. Basim, Ted S. Moise
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Publication number: 20140035061Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: ApplicationFiled: October 10, 2013Publication date: February 6, 2014Applicant: Texas Instruments IncorporatedInventors: Rajni J. AGGARWAL, Jau-Yuann YANG
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Patent number: 8609501Abstract: A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.Type: GrantFiled: April 19, 2012Date of Patent: December 17, 2013Assignee: Texas Instruments IncorporatedInventors: Weidong Tian, Ming-Yeh Chuang, Rajni J. Aggarwal
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Patent number: 8580631Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: GrantFiled: October 21, 2011Date of Patent: November 12, 2013Assignee: Texas Instruments IncorporatedInventors: Rajni J. Aggarwal, Jau-Yuann Yang
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Publication number: 20130065374Abstract: A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch.Type: ApplicationFiled: April 19, 2012Publication date: March 14, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Weidong Tian, Ming-Yeh Chuang, Rajni J. Aggarwal
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Patent number: 8377719Abstract: A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.Type: GrantFiled: November 30, 2011Date of Patent: February 19, 2013Assignee: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Rajni J. Aggarwal
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Publication number: 20120241907Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.Type: ApplicationFiled: May 31, 2012Publication date: September 27, 2012Applicant: Texas Instruments IncorporatedInventors: RAJNI J. AGGARWAL, SCOTT R. SUMMERFELT, GUL B. BASIM, TED S. MOISE
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Publication number: 20120098071Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajni J. Aggarwal, Jau-Yuann Yang
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Publication number: 20120077287Abstract: A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.Type: ApplicationFiled: November 30, 2011Publication date: March 29, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Scott R. Summerfelt, Rajni J. Aggarwal
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Patent number: 7968878Abstract: A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.Type: GrantFiled: August 7, 2009Date of Patent: June 28, 2011Assignee: Texas Instruments IncorporatedInventors: Rajni J. Aggarwal, YuGuo Wang
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Publication number: 20110084323Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.Type: ApplicationFiled: October 9, 2009Publication date: April 14, 2011Applicant: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Rajni J. Aggarwal, Shaoping Tang
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Publication number: 20110079878Abstract: An integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer. A method for forming an integrated circuit containing a ferroelectric capacitor, an underlying hydrogen barrier, and an overlying hydrogen barrier layer.Type: ApplicationFiled: September 24, 2010Publication date: April 7, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajni J. Aggarwal, Scott R. Summerfelt, Gul B. Basim, Ted S. Moise
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Publication number: 20100090340Abstract: An integrated circuit containing hydrogen permeable dummy vias configured in a linear or rectangular array and symmetrically positioned over a component in the integrated circuit. An integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components. A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Applicant: Texas Instruments IncorporatedInventors: Scott R. Summerfelt, Rajni J. Aggarwal
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Publication number: 20100032670Abstract: A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active areas to maximize a sensitivity to stress induced defects. The diode array is compatible with conventional electrical testing. Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) may be used to isolate individual stress induced defects. Variations in the gate configuration allow estimation of effects of circuit layout on formation of stress induced defects.Type: ApplicationFiled: August 7, 2009Publication date: February 11, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Rajni J. AGGARWAL, YuGuo WANG
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Patent number: 5346851Abstract: A quantum effect device implementation of the Shannon Decomposition Function in the form of a Shannon Cell is provided in which a first quantum dot logic unit (50) is coupled between the X input and the output of the Shannon Cell. A second quantum dot logic unit (52) is coupled between the Y input and the output of the Shannon Cell. The control input to the Shannon Cell is coupled to both the first and second quantum dot logic units (50 and 52) such that current flows through the appropriate quantum dot logic unit (50 or 52) depending upon the logic state of the control input.Type: GrantFiled: November 20, 1992Date of Patent: September 13, 1994Assignee: Texas Instruments IncorporatedInventors: John N. Randall, Gary A. Frazier, Rajni J. Aggarwal