Patents by Inventor Rajshree Chabukswar

Rajshree Chabukswar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103914
    Abstract: In one embodiment, a processor includes: a plurality of cores to execute instructions; at least one monitor coupled to the plurality of cores to measure at least one of power information, temperature information, or scalability information; and a control circuit coupled to the at least one monitor. Based at least in part on the at least one of the power information, the temperature information, or the scalability information, the control circuit is to notify an operating system that one or more of the plurality of cores are to transition to a forced idle state in which non-affinitized workloads are prevented from being scheduled. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Russell J. Fenger, Rajshree A. Chabukswar, Benjamin Graniello, Monica Gupta, Guy M. Therien, Michael W. Chynoweth
  • Patent number: 11934249
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Zhongsheng Wang, Chris Binns, Deepak Samuel Kirubakaran, Ashraf H Wadaa, Rajshree Chabukswar, Ahmed Shams, Sze Ling Yeap, Refael Mizrahi, Nicholas Klein
  • Publication number: 20240045490
    Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 8, 2024
    Inventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
  • Patent number: 11775047
    Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
  • Publication number: 20230305742
    Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.
    Type: Application
    Filed: June 1, 2023
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
  • Patent number: 11693588
    Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
  • Publication number: 20230092268
    Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 23, 2023
    Inventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
  • Publication number: 20230091167
    Abstract: An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Toby Opferman, Michael W. Chynoweth, Rajshree A. Chabukswar, Vijay C. Bahirji
  • Patent number: 11593154
    Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Ahmad Samih, Rajshree Chabukswar, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, Monica Gupta, Christine M. Lin
  • Publication number: 20220374066
    Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 24, 2022
    Inventors: JIANFANG ZHU, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
  • Patent number: 11436118
    Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Omer Barak, Rajshree Chabukswar, Russell Fenger, Eugene Gorbatov, Monica Gupta, Julius Mandelblat, Nir Misgav, Efraim Rotem, Ahmad Yasin
  • Patent number: 11422616
    Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Jianfang Zhu, Deepak Samuel Kirubakaran, Raoul Rivas Toledano, Chee Lim Nge, Rajshree Chabukswar, James Hermerding, II, Sudheer Nair, William Braun, Zhongsheng Wang, Russell Fenger, Udayan Kapaley
  • Publication number: 20220221925
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Zhongsheng Wang, Chris Binns, Deepak Samuel Kirubakaran, Ashraf H Wadaa, Rajshree Chabukswar, Ahmed Shams, Sze Ling Yeap, Refael Mizrahi, Nicholas Klein
  • Publication number: 20220206862
    Abstract: Embodiments of apparatuses, methods, and systems for resource control based on software priority are described. In embodiments, an apparatus includes resource sharing hardware and multiple cores. The resource sharing hardware is to share the shared resource among the cores. A first core includes first execution circuitry to execute multiple threads. The first core also includes registers programmable by software. A first register is to store a first identifier of a first thread and a first priority tag to indicate a first priority of the first thread relative to a second priority of a second thread. A second register to store a second identifier of the second thread and a second priority tag to indicate the second priority of the second thread relative to the first priority of the first thread. The resource sharing hardware is to use the first priority and the second priority to control access to the shared resource by the first thread and the second thread.
    Type: Application
    Filed: December 25, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Monica Gupta, Russell Fenger, Andrew J. Herdrich, Rajshree Chabukswar, Jumnit Hong, Sneha Gohad
  • Publication number: 20220197367
    Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Deepak S Kirubakaran, Ramakrishnan Sivakumar, Russell Fenger, Monica Gupta, Jianwei Dai, Premanand Sakarda, Guy Therien, Rajshree Chabukswar, Chad Gutierrez, Renji Thomas
  • Publication number: 20220113781
    Abstract: Methods and apparatus for bi-directional control of computing unit frequency are disclosed. An example apparatus to control a frequency of a computing unit includes instructions, memory in the apparatus, and processor circuitry. The processor circuitry is to determine a performance hint from a first register, the performance hint corresponding to a requested performance of the computing unit for executing a thread associated with software, determine power and performance (PnP) statistics pertaining to the thread from a second register, control the frequency of the computing unit based on the performance hint and the PnP statistics, and provide a pressure of the computing unit to the software.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Jianwei Dai, Jianfang Zhu, Ivan Chen, Deepak Samuel Kirubakaran, Rajshree Chabukswar, Richard Winterton, Houfei Chen
  • Publication number: 20210304096
    Abstract: Techniques and mechanisms to dynamically prioritize communication of a data flow based on an indication of a user's interest in a particular task. In an embodiment, data flows correspond to different respective tasks that are executed with a host operating system. An output of a human interface device indicates whether, at a particular time, a user of a computer device is interested in one particular task over another task. Where greater user interest in a first task is indicated, a first packet type corresponding to the first task is assigned a relatively high priority, as compared to a second packet type which corresponds to a second task. Based on the priority, a resource of the network interface is selectively made available (or prevented from being made available) for the communication of a given packet. In another embodiment, the resource includes a queue of the network interface.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Deepak Samuel Kirubakaran, Venkateshan Udhayan, Atsuo Kuwahara, Rajshree Chabukswar, Ramakrishnan Sivakumar, William Braun, Noam Ginsburg, Jianfeng Zhu, Paul Diefenbaugh, Kristoffer Fleming, Keerthanna Mohan
  • Publication number: 20210303054
    Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Inventors: JIANFANG ZHU, DEEPAK SAMUEL KIRUBAKARAN, RAOUL RIVAS TOLEDANO, CHEE LIM NGE, RAJSHREE CHABUKSWAR, JAMES HERMERDING, II, SUDHEER NAIR, WILLIAM BRAUN, ZHONGSHENG WANG, RUSSELL FENGER, UDAYAN KAPALEY
  • Publication number: 20210294641
    Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Deepak Samuel Kirubakaran, William A. Braun, Rajshree A. Chabukswar, Leigh Davies, Russell J. Fenger, Alexander Gendler, Raoul V. Rivas Toledano, Eliezer Weissmann
  • Patent number: 11093278
    Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 17, 2021
    Assignee: INTEL CORPORATION
    Inventors: Michael Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jeremy Shrall