Patents by Inventor Rajshree Chabukswar
Rajshree Chabukswar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210200656Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors.Type: ApplicationFiled: December 27, 2019Publication date: July 1, 2021Inventors: ELIEZER WEISSMANN, Omer Barak, Rajshree Chabukswar, Russell Fenger, Eugene Gorbatov, Monica Gupta, Julius Mandelblat, Nir Misgav, Efraim Rotem, Ahmad Yasin
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Publication number: 20210200580Abstract: Embodiments of apparatuses, methods, and systems for performance monitoring in heterogenous systems are described. In an embodiment, an apparatus includes a plurality of performance counters to generate a plurality of unweighted event counts; a weights storage to store a plurality of weight values, each weight value corresponding to an unweighted event count; a plurality of weighting units, each weighting unit to weight a corresponding unweighted event count based on a corresponding weight value to generate one of a plurality of weighted event counts; and a work counter to receive the weighted event counts and generate a measured work amount.Type: ApplicationFiled: December 28, 2019Publication date: July 1, 2021Applicant: Intel CorporationInventors: Ahmad Yasin, Julius Mandelblat, Eliezer Weissmann, Rajshree A. Chabukswar, Michael W. Chynoweth
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Publication number: 20200249866Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.Type: ApplicationFiled: April 21, 2020Publication date: August 6, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Publication number: 20200210178Abstract: A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.Type: ApplicationFiled: March 6, 2020Publication date: July 2, 2020Inventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
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Publication number: 20200201671Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Applicant: Intel CorporationInventors: AHMAD SAMIH, RAJSHREE CHABUKSWAR, Russell Fenger, Shadi Khasawneh, Vijay Dhanraj, Muhammad Abozaed, Mukund Ramakrishna, Atsuo Kuwahara, Guruprasad Settuvalli, Eugene Gorbatov, MONICA GUPTA, CHRISTINE M. LIN
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Patent number: 10656697Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: GrantFiled: March 5, 2018Date of Patent: May 19, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Patent number: 10649688Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: GrantFiled: November 1, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Ahmad Yasin, Michael Chynoweth, Rajshree Chabukswar, Muhammad Taher
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Publication number: 20200142629Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: Ahmad YASIN, Michael CHYNOWETH, Rajshree CHABUKSWAR, Muhammad TAHER
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Publication number: 20200125396Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.Type: ApplicationFiled: June 30, 2017Publication date: April 23, 2020Inventors: Michael Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jeremy Shrall
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Patent number: 10592244Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.Type: GrantFiled: February 2, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
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Patent number: 10445204Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.Type: GrantFiled: September 25, 2015Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Richard B. O'Connor, Beeman C. Strong, Michael W. Chynoweth, Rajshree A. Chabukswar
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Publication number: 20190050041Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: ApplicationFiled: March 5, 2018Publication date: February 14, 2019Inventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Publication number: 20190041950Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.Type: ApplicationFiled: March 28, 2018Publication date: February 7, 2019Inventors: Michael W. Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jason W. Brandt, Alexander Gendler, Ahmad Yasin, Patrick Konsor, Sneha Gohad, William Freelove
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Publication number: 20180314289Abstract: A processor includes a plurality of processing engines and a throttling circuit. The throttling circuit may be to: detect an execution of a pause instruction in a first processing engine operating at a first frequency level; in response to the execution of the pause instruction, increment a cycle counter to count a number of cycles that the first processing engine is paused by executing the pause instruction; and in response to a determination that the cycle counter has reached a first threshold level, change an operating frequency of the first processing engine from the first frequency level to a second frequency level, wherein the second frequency level is lower than the first frequency level.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: RAJSHREE A. CHABUKSWAR, MICHAEL W. CHYNOWETH, ELIEZER WEISSMANN, JEREMY J. SHRALL, GREG D. KAINE
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Publication number: 20180217839Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.Type: ApplicationFiled: February 2, 2017Publication date: August 2, 2018Inventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
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Patent number: 9910475Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: GrantFiled: December 23, 2014Date of Patent: March 6, 2018Assignee: Intel CorporationInventors: Tsvika Kurts, Beeman C. Strong, Richard B. O'Connor, Michael W. Chynoweth, Rajshree A. Chabukswar, Avner Lottem, Itamar Kazachinsky, Michael Mishaeli, Anthony Wojciechowski, Vikas R. Vasisht
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Patent number: 9626274Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.Type: GrantFiled: December 23, 2014Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett
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Publication number: 20170090925Abstract: A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Richard B. O'Connor, Beeman C. Strong, Michael W. Chynoweth, Rajshree A. Chabukswar
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Publication number: 20160179650Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: Ahmad Yasin, Rajshree A. Chabukswar, Ofer Levy, Michael W. Chynoweth, Charlie J. Hewett
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Publication number: 20160179166Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Inventors: TSVIKA KURTS, BEEMAN C. STRONG, RICHARD B. O'CONNOR, MICHAEL W. CHYNOWETH, RAJSHREE A. CHABUKSWAR, AVNER LOTTEM, ITAMAR KAZACHINSKY, MICHAEL MISHAELI, ANTHONY WOJCIECHOWSKI, VIKAS R. VASISHT