Patents by Inventor Rak-Hwan Kim

Rak-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546841
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 28, 2020
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Ralph Nuzzo, Hoon-sik Kim, Eric Brueckner, Sang Il Park, Rak Hwan Kim
  • Patent number: 10418326
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Ji Jung, Rak Hwan Kim, Byung Hee Kim, Young Hun Kim, Gyeong Yun Han
  • Patent number: 10388563
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung
  • Patent number: 10332791
    Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Yun Jeon, Rak-Hwan Kim, Byung-Hee Kim, Kyoung-Hee Nam, Jong-Jin Lee, Jae-Won Hwang
  • Publication number: 20190189744
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20190189540
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Tsukasa MATSUDA, Rak-Hwan KIM, Byung-Hee KIM, Nae-In LEE, Jong-Jin LEE
  • Patent number: 10217820
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20180359850
    Abstract: Described herein are flexible and stretchable LED arrays and methods utilizing flexible and stretchable LED arrays. Assembly of flexible LED arrays alongside flexible plasmonic crystals is useful for construction of fluid monitors, permitting sensitive detection of fluid refractive index and composition. Co-integration of flexible LED arrays with flexible photodetector arrays is useful for construction of flexible proximity sensors. Application of stretchable LED arrays onto flexible threads as light emitting sutures provides novel means for performing radiation therapy on wounds.
    Type: Application
    Filed: March 30, 2018
    Publication date: December 13, 2018
    Inventors: John A. ROGERS, Rak-Hwan KIM, Dae-Hyeong KIM, David L. KAPLAN, Fiorenzo G. OMENETTO
  • Publication number: 20180166334
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Application
    Filed: August 3, 2017
    Publication date: June 14, 2018
    Inventors: Rak Hwan KIM, Byung Hee KIM, Sang Bom KANG, Jong Jin LEE, Eun Ji JUNG
  • Publication number: 20180158781
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 7, 2018
    Inventors: Eun Ji Jung, Rak Hwan Kim, Byung Hee Kim, Young Hun Kim, Gyeong Yun Han
  • Publication number: 20180158730
    Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
    Type: Application
    Filed: November 7, 2017
    Publication date: June 7, 2018
    Inventors: Ho-Yun Jeon, Rak-Hwan Kim, Byung-Hee Kim, Kyoung-Hee Nam, Jong-Jin Lee, Jae-Won Hwang
  • Patent number: 9991203
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung
  • Patent number: 9936574
    Abstract: Described herein are flexible and stretchable LED arrays and methods utilizing flexible and stretchable LED arrays. Assembly of flexible LED arrays alongside flexible plasmonic crystals is useful for construction of fluid monitors, permitting sensitive detection of fluid refractive index and composition. Co-integration of flexible LED arrays with flexible photodetector arrays is useful for construction of flexible proximity sensors. Application of stretchable LED arrays onto flexible threads as light emitting sutures provides novel means for performing radiation therapy on wounds.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: April 3, 2018
    Assignees: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS, TRUSTEES OF TUFTS COLLEGE
    Inventors: John A. Rogers, Rak-Hwan Kim, Dae-Hyeong Kim, David L. Kaplan, Fiorenzo G. Omenetto
  • Publication number: 20170358519
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.
    Type: Application
    Filed: August 4, 2017
    Publication date: December 14, 2017
    Inventors: Jin-Nam Kim, Tsukasa Matsuda, Rak-Hwan Kim, Byung-Hee Kim, Nae-In Lee, Jong-Jin Lee
  • Publication number: 20170294337
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 9773699
    Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Jin Lee, Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Tsukasa Matsuda, Wan-Soo Park, Nae-In Lee, Jae-Won Chang, Eun-Ji Jung, Jeong-Ok Cha, Jae-Won Hwang, Jung-Ha Hwang
  • Patent number: 9728604
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20170200707
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Applicant: The Board of Trustees of the University of Illinois
    Inventors: John A. ROGERS, Ralph NUZZO, Hoon-sik KIM, Eric BRUECKNER, Sang Il PARK, Rak Hwan KIM
  • Publication number: 20170133317
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 11, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan KIM, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung
  • Patent number: 9647171
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: May 9, 2017
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Ralph Nuzzo, Hoon-sik Kim, Eric Brueckner, Sang Il Park, Rak Hwan Kim