Abstract: A substrate includes structures formed on a growth surface of the substrate. The structures are formed in a multi-periodic pattern, which includes a first plurality of groups of structures. Each group of structures has a characteristic spacing between adjacent structures in the group. Each group of structures is separated from an adjacent group of structures by a second characteristic spacing. The second characteristic spacing is at least 1.5 times larger than the first characteristic spacing.

Abstract: A hydrocolloid or aqueous solution comprising a poly alpha-1,3-glucan ether compound is disclosed having a viscosity of at least about 10 centipoise (cPs). The poly alpha-1,3-glucan ether compound in these compositions has a degree of substitution of about 0.05 to about 3.0. Also disclosed is a method for increasing the viscosity of a hydrocolloid or aqueous composition using a poly alpha-1,3-glucan ether compound.

Abstract: A heterostructure with reduced optical losses is disclosed. The heterostructure includes a set of n-type layers; an active region that generates radiation at a peak emitted wavelength; and a set of p-type layers located adjacent to the active region. A reflective structure can be located adjacent to the set of p-type layers. A thickness of the set of p-type layers can be configured to promote constructive interference of the reflected radiation with radiation emitted by the active region in a direction toward the set of n-type layers.

Abstract: A solution for fabricating a semiconductor structure and the corresponding semiconductor structure are provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

Abstract: The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having late wilt (LW) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to LW. The disclosure also provides markers associated with LW resistance loci for introgressing these loci into elite germplasm in a breeding program, thus producing novel LW resistant germplasm.

Abstract: The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having late wilt (LW) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to LW. The disclosure also provides markers associated with LW resistance loci for introgressing these loci into elite germplasm in a breeding program, thus producing novel LW resistant germplasm.

Abstract: A heterostructure with reduced optical losses is disclosed. The heterostructure includes a set of n-type layers; an active region that generates radiation at a peak emitted wavelength; and a set of p-type layers located adjacent to the active region. A reflective structure can be located adjacent to the set of p-type layers. A thickness of the set of p-type layers can be configured to promote constructive interference of the reflected radiation with radiation emitted by the active region in a direction toward the set of n-type layers.

Abstract: A heterostructure with reduced optical losses is disclosed. The heterostructure includes a set of n-type layers; an active region that generates radiation at a peak emitted wavelength; and a set of p-type layers located adjacent to the active region. A reflective structure can be located adjacent to the set of p-type layers. A thickness of the set of p-type layers can be configured to promote constructive interference of the reflected radiation with radiation emitted by the active region in a direction toward the set of n-type layers.

Abstract: A method including: in a network element that includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element and a utilization management process running on the network element, the utilization management process performing operations including: obtaining a plurality of entries of the one or more hardware memory resources representing utilization of the one or more hardware memory resources by network traffic passing through the network element; sorting the plurality of entries of the one or more hardware memory resources by statistics associated with the network traffic passing through the network element to produce sorted entries; and sending the extracted to a network management application for display is disclosed. An apparatus and one or more non-transitory computer readable storage media to execute the method are also provided.

Abstract: The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having late wilt (LW) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to LW. The disclosure also provides markers associated with LW resistance loci for introgressing these loci into elite germplasm in a breeding program, thus producing novel LW resistant germplasm.

Abstract: The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having late wilt (LW) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to LW. The disclosure also provides markers associated with LW resistance loci for introgressing these loci into elite germplasm in a breeding program, thus producing novel LW resistant germplasm.

Abstract: A network element includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element. A utilization management process runs on the network element to perform operations including obtaining utilization data representing utilization of the one or more hardware memory resources, and analyzing the utilization data of the one or more hardware memory resources to produce summarized utilization data.

Abstract: A method including: in a network element that includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element and a utilization management process running on the network element, the utilization management process performing operations including: obtaining a plurality of entries of the one or more hardware memory resources representing utilization of the one or more hardware memory resources by network traffic passing through the network element; sorting the plurality of entries of the one or more hardware memory resources by statistics associated with the network traffic passing through the network element to produce sorted entries; and sending the extracted to a network management application for display is disclosed. An apparatus and one or more non-transitory computer readable storage media to execute the method are also provided.

Abstract: A method including: in a network element that includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element and a utilization management process running on the network element, the utilization management process performing operations including: obtaining a plurality of entries of the one or more hardware memory resources representing utilization of the one or more hardware memory resources by network traffic passing through the network element; sorting the plurality of entries of the one or more hardware memory resources by statistics associated with the network traffic passing through the network element to produce sorted entries; and sending the extracted to a network management application for display is disclosed. An apparatus and one or more non-transitory computer readable storage media to execute the method are also provided.

Abstract: A method including: in a network element that includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element and a utilization management process running on the network element, the utilization management process performing operations including: obtaining a plurality of entries of the one or more hardware memory resources representing utilization of the one or more hardware memory resources by network traffic passing through the network element; sorting the plurality of entries of the one or more hardware memory resources by statistics associated with the network traffic passing through the network element to produce sorted entries; and sending the extracted to a network management application for display is disclosed. An apparatus and one or more non-transitory computer readable storage media to execute the method are also provided.

Abstract: The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having late wilt (LW) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to LW. The disclosure also provides markers associated with LW resistance loci for introgressing these loci into elite germplasm in a breeding program, thus producing novel LW resistant germplasm.

Abstract: A network element includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element. A utilization management process runs on the network element to perform operations including obtaining utilization data representing utilization of the one or more hardware memory resources, and analyzing the utilization data of the one or more hardware memory resources to produce summarized utilization data.

Abstract: A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region. In a further embodiment, a transistor fabrication method includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area.

Abstract: The presently preferred embodiment of the invention provides a memory structure that eliminates the thick gate associated with the offset of the FAMOS transistor and reduces the standard 225 angstrom offset to a 100 angstrom offset required for FN tunnelling. The 100 angstrom offset is realized uniformly underneath the entire area of the floating poly. The invention uses transistors each having a 100 angstrom offset to realize both erase and programming functions. The present invention realizes an erasing feature through an erase transistor and an ERL line. However, the programming of the cell will be realized through the programming transistor. As a result, a double poly flash cell will function like an EEPROM. This functioning eliminates the hot electron tunnelling required to program conventional double poly flash cells and results in a significant reduction in chip real estate. The reduction allows the present invention to be scaled to next generation architectures.

Abstract: An integrated circuit based on submicron technology is disclosed herein along with the way in which it is formed. The integrated circuit is comprised of an arrangement of different substances which are combined to form its body structure and which define within the body structure an array of electronic components including a diamond thin film coated trench arrangement. In one embodiment disclosed herein, the array of electronic component includes two such components which are in close proximity to and must be electrically isolated from one another and the diamond thin film coated trench arrangement serves to electrically isolate these two components from each other. In a second embodiment, the diamond thin film coated trench is specifically designed to serve as a capacitor forming part of, for example, a DRAM, a mixed signal circuit or a neuro-fuzzy circuit.