Abstract: An arrangement for reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in a specific area. The arrangement also includes an arrangement for removing the holes from the containment area. A method of reducing the erratic operation of a non-volatile memory cell caused by the accumulation of holes at a specific location within the cell during the electrical erasing of the cell includes the step of providing a layer of hole confinement material positioned at the specific location the holes accumulate for containing the holes in the layer of hole confinement material.

Abstract: A thin film mask for use in an X-ray lithographic process is disclosed herein along with a method of making the mask which is comprised of a diamond thin film layer supported on one surface of an X-ray transparent non-diamond substrate, for example silicon. A predetermined pattern of ions of a substance opaque to X-rays, for example a heavy atomic number substance such as gold, tungsten or cesium, is introduced into the diamond thin film layer as opposed to being deposited thereon. In one embodiment disclosed herein, this is accomplished by means of ion implantation, and in a second embodiment by means of an ion beam direct write device.

Abstract: A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400.ANG. thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100.ANG. thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600.ANG. thick, a silicon dioxide layer about 20-50.ANG. thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000.ANG. thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.