Patents by Inventor Rakesh Kumar

Rakesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240329823
    Abstract: A system for modulating a graphical user interface (GUI) comprises a user device in communication with a system controller. The user device comprises a display interface for displaying the GUI. The GUI defines a frame boundary a GUI size, and comprises content displayed via the display interface. The user device, the system controller and/or a synergistic combination thereof execute computer implementable steps for detecting a real-time status, determining the real-time status, and modulating the GUI on the basis of the determined real-time status. The real-time status is selected from the group consisting of a device user status, a device status, an auxiliary device status, a content status, and a combination thereof. The real-time status is determined based on status criteria stored within the memory of the system controller and/or the user device.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Inventors: Rajeev KUMAR, Rakesh KUMAR
  • Patent number: 12101601
    Abstract: A microelectromechanical system microphone includes a piezoelectric diaphragm, upper inner electrodes and upper outer electrodes disposed on an upper surface of the diaphragm, and lower inner electrodes and lower outer electrodes disposed on a lower surface of the diaphragm. The diaphragm is divided into a plurality of sectors, a first of the sectors including an inner and an outer upper electrode physically disconnected from an inner and an outer upper electrode on a second sector adjacent to the first sector, and an inner and an outer lower electrode physically disconnected from an inner and an outer lower electrode on the second sector. A first via extends between and electrically couples the upper and lower inner electrodes of the first sector and a first bond pad. A second via extends between and electrically couples the upper and lower outer electrodes of the second sector and a second bond pad.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: September 24, 2024
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Guofeng Chen, You Qian, Rakesh Kumar, Michael Jon Wurtz, Humberto Campanella-Pineda
  • Patent number: 12101253
    Abstract: In general, techniques are described for a computing device including a virtual router, a pod comprising a container, and a network plugin. The virtual router includes a virtual router agent. The network plugin includes processing circuitry configured to receive, from the virtual router agent, an indication of an interface type for a virtual network for the pod and to configure, for the pod, a virtual network interface having the interface type, the virtual network interface for communicating on the virtual network.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: September 24, 2024
    Assignee: Juniper Networks, Inc.
    Inventors: Shailender Sharma, Yuvaraja Mariappan, Rakesh Kumar Reddy Varimalla, Jude Pragash Vedam
  • Patent number: 12092690
    Abstract: The present disclosure relates to an apparatus (100) for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry (102) that is interfaced to a target integrated circuit (IC) (106) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (104-1, 104-2) operating in master mode and slave mode. The controller circuitry (102) operates the one or more SPI devices (104-1, 104-2) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: September 17, 2024
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Rakesh Kumar Polasa, Alagesan Mani
  • Patent number: 12090195
    Abstract: The present disclosure relates to a fully liquid immunogenic composition comprising a combination of antigens/immunogens. The immunogenic composition comprises optimum amount of antigens/immunogens to confer protection against a number of diseases. The composition exhibits improved immunogenicity and stability. A process for preparing the vaccine composition is also disclosed.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 17, 2024
    Assignee: Serum Institute of India Private Limited
    Inventors: Inder Jit Sharma, Rakesh Kumar, Jaganathan Semburakkiannan Kilvani, Manohar Doddapaneni, Anil Vyankatrao Shitole
  • Patent number: 12092458
    Abstract: A system of a motor vehicle includes a radar unit for generating a radar signal associated with a target positioned about the vehicle. The system further includes a tracker generating a tracker signal associated with a radar heading and a doppler based on the radar signal. The system further includes a wheel speed sensor for generating a wheel speed signal associated with a velocity of the vehicle. The system further includes a gyroscope for generating a gyro signal associated with a measured yaw rate. The system further includes a computer having a processor and a computer readable medium. The processor is programmed to determine a gyro drift and a corrected yaw rate while the vehicle is in motion, with the gyro drift and the corrected yaw rate being based on at least the radar heading, the doppler effect, and the velocity of the vehicle, and the measured yaw rate.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: September 17, 2024
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Brent Navin Roger Bacchus, Rakesh Kumar, Curtis L. Hay
  • Publication number: 20240303132
    Abstract: A method and a system for providing a combination of optimal and stable instances are disclosed. The method includes receiving a configuration information of an application for execution; identifying parameters related to the application of user; identifying a set of optimal instances based on the identified parameters; fetching a data of historical spot instance(s) from a host platform; predicting a stability score for each of the optimal spot instances based on at least the data of the historical spot instance(s); predicting an intermediate set of optimal and stable spot instances from the at least one optimal spot instance based on the stability score of the optimal spot instances; and predicting the combination of optimal and stable instances, based on at least on a cost factor and based on at least one of the intermediate set of optimal and stable spot instances, and a set of optimal on-demand instances.
    Type: Application
    Filed: April 19, 2023
    Publication date: September 12, 2024
    Applicant: JPMorgan Chase Bank, N.A.
    Inventors: Rakesh Kumar KASHYAP, Abdul Subhan Shoukat GHOUSE, Srileka VIJAYAKUMAR, Faraz ZAIDI, Keerthi CHIVUKULA
  • Publication number: 20240303860
    Abstract: A method, apparatus, and system for providing orientation and location estimates for a query ground image include determining spatial-aware features of a ground image and applying a model to the determined spatial-aware features to determine orientation and location estimates of the ground image.
    Type: Application
    Filed: March 8, 2024
    Publication date: September 12, 2024
    Inventors: Niluthpol MITHUN, Kshitij MINHAS, Han-Pang CHIU, Taragay OSKIPER, Mikhail SIZINTSEV, Supun SAMARASEKERA, Rakesh KUMAR
  • Patent number: 12085972
    Abstract: Systems and methods for sampled band-gap reference voltage generators are described. An embodiment includes a band-gap reference voltage generator circuit that includes: a first load transistor, a second load transistor where the gates of the first and second load transistors are connected, a first bipolar transistor, a second bipolar transistor, where the bases of the first and second bipolar transistors are connected, a first capacitor where a first terminal of the first capacitor is connected to the emitter of the first bipolar transistor through a first switch and a second terminal of the first capacitor is connected to the emitter of the second bipolar transistor through a second switch.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: September 10, 2024
    Assignee: Mixed-Signal Devices Inc.
    Inventors: Rakesh Kumar Palani, Srikar Bhagavatula
  • Patent number: 12081336
    Abstract: Techniques are described for capturing dropped packets and creating modified dropped packets with drop information associated with the dropped packets to provide greater details of the dropped packets for further analysis and/or serviceability. For example, a computing device comprises an internal communication channel, a process executing in user space, and a virtual router. The virtual router comprises, for example, processing circuitry and a drop interface to the internal communication channel, wherein the virtual router is configured to: receive a packet; in response to determining the packet is to be dropped, creating a modified dropped packet to include drop information associated with the packet; and provide the modified dropped packet to the drop interface to communicate the modified dropped packet via the internal communication channel to the process.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: September 3, 2024
    Assignee: JUNIPER NETWORKS, INC.
    Inventors: Kiran K N, Yashika Badaya, Rakesh Kumar Reddy Varimalla
  • Publication number: 20240291761
    Abstract: In general, techniques are described for dynamically load balancing among processing cores that a virtual router of a computing device uses to process network traffic associated with different workloads executing on the computing device. In some examples, a first computing device may assign, based on one or more metrics that indicate processing cores utilization or that indicate network traffic processing requirements for a workload that is to execute on a second computing device, network traffic processing for the workload to a first processing core of a plurality of processing cores of the second computing device. A virtual router, executing on the first processing core based on the assigning, may process network traffic for the workload.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Inventors: Kiran K N, Shailender Sharma, Rakesh Kumar Reddy Varimalla
  • Patent number: 12068602
    Abstract: A control system for a power distribution grid including an electrical distribution circuit includes a processor configured to perform operations including constructing a grid model comprising edges and nodes representing assets and transmission paths of the power distribution grid, generating an analysis of an operation of the power distribution grid over a predetermined time duration, determining a plurality of constraint violations based on the analysis of the operation of the power distribution grid within the predetermined time duration, generating a plurality of alterations to the power distribution grid, respective ones of the plurality of alterations resolving at least one of the constraint violations, selecting a first alteration of the plurality of alterations to the power distribution grid responsive to determining that the selected first alteration resolves at least two of the plurality of constraint violations, and autonomously implementing the first alteration to the power distribution grid.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 20, 2024
    Assignee: Duke Energy Corporation
    Inventors: W R M Anuja Ratnayake, Daniel Woodall, Andrew Kling, Gerard Rendell, Jacob A. Richardson, Miguel Armando Sanda, Jose Martin Cardenas, John Templeton Pressley, Rakesh Kumar Belchandan
  • Patent number: 12062174
    Abstract: A method, machine readable medium and system for semantic segmentation of 3D point cloud data includes determining ground data points of the 3D point cloud data, categorizing non-ground data points relative to a ground surface determined from the ground data points to determine legitimate non-ground data points, segmenting the determined legitimate non-ground and ground data points based on a set of common features, applying logical rules to a data structure of the features built on the segmented determined non-ground and ground data points based on their spatial relationships and incorporated within a machine learning system, and constructing a 3D semantics model from the application of the logical rules to the data structure.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: August 13, 2024
    Assignee: SRI International
    Inventors: Anil Usumezbas, Bogdan Calin Mihai Matei, Rakesh Kumar, Supun Samarasekera
  • Patent number: 12061629
    Abstract: Methods, systems and computer program products implementing hierarchical classification techniques are disclosed. A hierarchical classification system receives training data including labeled transaction records. The system determines tag sequences from the training data. The system clusters the tag sequences into clusters. The system determines a cluster-level classifier that is trained to predict a cluster for an input transaction record. The system determines a respective cluster-specific classifier for each cluster. The system trains the cluster-specific classifier to predict a label of entity of interest for an input transaction record, given a particular cluster. Upon receiving a test transaction record, the system first applies the cluster-level classifier to determine a particular cluster for the test transaction record, and then determines a label of entity of interest of the test transaction record by applying a cluster-specific classifier of that particular cluster.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: August 13, 2024
    Assignee: Yodlee, Inc.
    Inventors: Chirag Yadav, Divya James Athoopallil, Ganesh Patil, Rakesh Kumar Ranjan, Aparajita Choudhury Karimpana, Om Dadaji Deshmukh
  • Patent number: 12057829
    Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.
    Type: Grant
    Filed: June 16, 2023
    Date of Patent: August 6, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Abhinav Murali, Pradeep Kumar Sana, Sajin Mohamad, Harikrishna Chintarlapalli Reddy, Rakesh Kumar Sinha, Jibu Varghese K
  • Patent number: 12045109
    Abstract: The present disclosure provides a system and method for reception of BMC data in USB PD communication. The system comprises an analog block and a digital block with the digital block further comprising an idle detection mechanism, and a digital controller for rejecting noise and auto correcting of received BMC signal. The BMC data is typically processed by means of varied functions such as comparison by a threshold comparator on the analog block with programmable reference, and other components of the digital block so as to realize aspects such as noise filtering of BMC data by changing the reference dynamically based on comparison of the width of threshold comparator output signal with average signal widths which is computed during the preamble phase of USB PD communications.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 23, 2024
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Rakesh Kumar Polasa, Shubham Paliwal, Srivalli Kalyani Mandalapu, Vinay Sadrhalli Nagendra Patel
  • Publication number: 20240239751
    Abstract: Provided herein are improved processes for the preparation of a compound of Formula IX (AG-10). Also provided herein are pharmaceutically acceptable salts of Formula I and Formula Ib as well as crystalline types of Formula IX (AG-10). The processes described herein provide improved yields and efficiency, while the pharmaceutically acceptable salts and crystalline forms provide unexpected pharmacokinetic properties. Other features and aspects of the present disclosure will be apparent to a person of skill in the art upon reading the remainder of the specification.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 18, 2024
    Inventors: Pooran CHAND, Yogesh Kumar GUPTA, Rakesh Kumar KUMAWAT, Mamoun ALHAMADSHEH, Robert ZAMBONI
  • Patent number: 12037239
    Abstract: A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: July 16, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR SINGAPORE PTE. LTD.
    Inventors: You Qian, Humberto Campanella-Pineda, Rakesh Kumar
  • Publication number: 20240231788
    Abstract: A computer-implemented system for modulating a navigation graphical user interface during movement of a vehicle comprises a device with an interface and a controller with a memory. The memory comprises a positioning system application providing for real-time tracking of a position of the moving vehicle within a geographic location and determining a direction pathway towards a target location within the geographic location. The interface comprises a display for displaying the navigation graphical user interface. A system controller determines the geographic location of the device and of the moving vehicle via the positioning system application in the memory of the device and accessible thereto via the interface. A leader virtual vehicle image is generated within the navigation graphical user interface and is displayed via the device display. The virtual vehicle image is positioned ahead of the tracked position of the moving vehicle within the navigation pathway.
    Type: Application
    Filed: March 20, 2024
    Publication date: July 11, 2024
    Inventors: Rajeev KUMAR, Rakesh KUMAR
  • Publication number: 20240219464
    Abstract: The present disclosure relates to an apparatus (100) for joint test action group (JTAG) and scan emulation, the apparatus includes a controller circuitry (102) that is interfaced to a target integrated circuit (IC) (106) for testing the target IC, the controller circuitry having one or more serial peripheral interface (SPI) devices (104-1, 104-2) operating in master mode and slave mode. The controller circuitry (102) operates the one or more SPI devices (104-1, 104-2) to switch between a first mode and a second mode dynamically to emulate JTAG and scan test functionality. The controller circuitry facilitates reusing the one or more SPI devices located in the controller circuitry to emulate JTAG and scan test interface protocols without any additional hardware requirements.
    Type: Application
    Filed: April 28, 2023
    Publication date: July 4, 2024
    Inventors: Rakesh Kumar POLASA, Alagesan MANI