Abstract: A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

Abstract: A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

Abstract: A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball.

Abstract: Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.

Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.

Abstract: Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract: Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

Abstract: An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors.

Abstract: Design methodologies and techniques for significantly increasing logic density by stitching multiple reticles together are disclosed. The invention teaches various techniques to ensure continuity of interconnections and sealing mechanisms across the stitch region. The stitch extended device is readily scalable to allow quick transitions to next generation technologies.