Patents by Inventor Rak-Hwan Kim

Rak-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128347
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Publication number: 20240120274
    Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 11, 2024
    Inventors: Eui Bok LEE, Rak Hwan KIM, Jong Min BAEK, Moon Kyun SONG
  • Patent number: 11942427
    Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Yong Yoo, Jong Jin Lee, Rak Hwan Kim, Eun-Ji Jung, Won Hyuk Hong
  • Patent number: 11923426
    Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Won Kang, Tae-Yeol Kim, Jeong Ik Kim, Rak Hwan Kim, Jun Ki Park, Chung Hwan Shin
  • Patent number: 11881519
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Publication number: 20230020234
    Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Inventors: Seung Yong YOO, Jong Jin Lee, Rak Hwan Kim, Eun-Ji Jung, Won Hyuk Hong
  • Publication number: 20220319916
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 6, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun CHUNG, Joon Gon LEE, Rak Hwan KIM, Chung Hwan SHIN, Do Sun LEE, Nam Gyu CHO
  • Patent number: 11450607
    Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Yong Yoo, Jong Jin Lee, Rak Hwan Kim, Eun-Ji Jung, Won Hyuk Hong
  • Publication number: 20220285518
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Patent number: 11367651
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
  • Patent number: 11349007
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Gyu Cho, Rak Hwan Kim, Hyeok-Jun Son, Do Sun Lee, Won Keun Chung
  • Publication number: 20220130970
    Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.
    Type: Application
    Filed: July 6, 2021
    Publication date: April 28, 2022
    Inventors: Ji Won KANG, Tae-Yeol KIM, Jeong Ik KIM, Rak Hwan KIM, Jun Ki PARK, Chung Hwan SHIN
  • Publication number: 20210210613
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a fin-type pattern extending in a first direction; a gate electrode extending in a second direction over the fin-type pattern, the second direction being different from the first direction; spacers on sidewalls of the gate electrode; a capping structure on the gate electrode and the spacers, the capping structure including a first capping pattern and a second capping pattern, the second capping pattern being on the first capping pattern; and an interlayer insulating film surrounding sidewalls of each of the spacers and sidewalls of the capping structure, the interlayer insulating film being in contact with the first capping pattern.
    Type: Application
    Filed: September 9, 2020
    Publication date: July 8, 2021
    Inventors: Nam Gyu CHO, Rak Hwan KIM, Hyeok-Jun SON, Do Sun LEE, Won Keun CHUNG
  • Patent number: 11057991
    Abstract: Described herein are flexible and stretchable LED arrays and methods utilizing flexible and stretchable LED arrays. Assembly of flexible LED arrays alongside flexible plasmonic crystals is useful for construction of fluid monitors, permitting sensitive detection of fluid refractive index and composition. Co-integration of flexible LED arrays with flexible photodetector arrays is useful for construction of flexible proximity sensors. Application of stretchable LED arrays onto flexible threads as light emitting sutures provides novel means for performing radiation therapy on wounds.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 6, 2021
    Assignees: The Board of Trustees of the University of Illinois, Trustees of Tufts College
    Inventors: John A. Rogers, Rak-Hwan Kim, Dae-Hyeong Kim, David L. Kaplan, Fiorenzo G. Omenetto
  • Publication number: 20210090999
    Abstract: A semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes first and second valley areas that are spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first and second valley areas are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench that exposes at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley area.
    Type: Application
    Filed: June 4, 2020
    Publication date: March 25, 2021
    Inventors: Seung Yong YOO, Jong Jin Lee, Rak Hwan Kim, Eun-Ji Jung, Won Hyuk Hong
  • Publication number: 20210020500
    Abstract: A semiconductor device includes a first interlayer insulating film; a conductive connection structure provided in the first interlayer insulating film; a second interlayer insulating film provided on the first interlayer insulating film; a wiring structure provided in the second interlayer insulating film and connected to the conductive connection structure; and an insertion liner interposed between an upper surface of the conductive connection structure and the wiring structure, the insertion liner including carbon.
    Type: Application
    Filed: June 16, 2020
    Publication date: January 21, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Keun Chung, Joon Gon Lee, Rak Hwan Kim, Chung Hwan Shin, Do Sun Lee, Nam Gyu Cho
  • Patent number: 10734309
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Tsukasa Matsuda, Rak-Hwan Kim, Byung-Hee Kim, Nae-In Lee, Jong-Jin Lee
  • Patent number: 10700164
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10546841
    Abstract: Described herein are printable structures and methods for making, assembling and arranging electronic devices. A number of the methods described herein are useful for assembling electronic devices where one or more device components are embedded in a polymer which is patterned during the embedding process with trenches for electrical interconnects between device components. Some methods described herein are useful for assembling electronic devices by printing methods, such as by dry transfer contact printing methods. Also described herein are GaN light emitting diodes and methods for making and arranging GaN light emitting diodes, for example for display or lighting systems.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: January 28, 2020
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: John A. Rogers, Ralph Nuzzo, Hoon-sik Kim, Eric Brueckner, Sang Il Park, Rak Hwan Kim
  • Patent number: 10418326
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film on a substrate, the interlayer insulating film including an opening, a barrier conductive film extending along a sidewall of the opening and a bottom surface exposed by the opening, a first film disposed on the barrier conductive film and in the opening, and the first film including cobalt, and a conductive liner on the barrier conductive film, the conductive liner extending along a portion of a side all of the opening and including a metal other than cobalt.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun Ji Jung, Rak Hwan Kim, Byung Hee Kim, Young Hun Kim, Gyeong Yun Han