Abstract: In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular ? the number of inputs of the test unit (3) that are contained in the base of a cone (5).

Abstract: A test apparatus includes a signal source that generates a radio-frequency test signal and is connected to the input connection of an arrangement. The arrangement simultaneously supplies an electrical radio-frequency signal to a plurality of receivers and via a plurality of distribution lines. Each distribution line includes an end with an output connection that applies the power-matched test signal to a respective external component.

Abstract: A method of manufacturing an optical element includes testing the optical element by using an interferometer optics generating a beam of measuring light illuminating only a sub-aperture of the tested optical element. The interferometer optics comprises a hologram. Results of the sub-aperture measurement are stitched together to obtain a measuring result with respect to the full surface of the optical element. Further, a method of calibrating the interferometer optics includes performing an interferometric measurement using a calibrating optics having a hologram covering only a sub-aperture of the full cross section of the beam of measuring light generated by the interferometer optics and stitching together the sub-aperture measurements to obtain a result indicative for the full cross section of the interferometer optics.

Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Abstract: Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple the internal test signal to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.

Abstract: An integrated circuit includes at least one input and output circuit including: a signal terminal that provides an external contact; a protective circuit coupled to the signal terminal; an input driver and/or an output driver coupled to the signal terminal via the protective circuit; and an additional circuit including a first input coupled to the signal terminal via the protective circuit, and an output that provides a test value for operation of the input and output circuit.

Abstract: A diffractive optical element contains a multiplicity of binary blazed diffraction structures, which substantially extend mutually parallel in a longitudinal direction. Perpendicularly to the longitudinal direction, the diffraction structures have a width g which is greater than the effective wavelength of electromagnetic radiation for which the diffractive optical element is designed. The diffraction structures respectively comprise a series of individual substructures, which produce a blaze effect and have a maximum extent p in the longitudinal direction which is less than the effective wavelength of the electromagnetic radiation, at least on average over a diffraction structure. In a plan view, the individual substructures respectively have the shape of a closed geometrical surface, which has an extent parallel to the longitudinal direction that varies perpendicularly to the longitudinal direction.

Abstract: A test apparatus includes a signal source that generates a radio-frequency test signal and is connected to the input connection of an arrangement. The arrangement simultaneously supplies an electrical radio-frequency signal to a plurality of receivers and via a plurality of distribution lines. Each distribution line includes an end with an output connection that applies the power-matched test signal to a respective external component.

Abstract: An electronic element, test system and method of testing an electronic circuit are provided. The electronic circuit has input and output terminals. The input terminals receive a test signal sequence to test the electronic circuit. Actual value signals of a 3-value logic of the electronic circuit are provided at the output terminals in response to the test signal sequence. A comparator circuit has first and second input terminals and an output terminal. Each of the output terminals of the electronic circuit are coupled to a first input terminal. The second input terminals receive desired value signals. The comparator circuit compares the actual value signals with the desired value signals and provides the comparison to the output terminal of the comparator circuit.

Abstract: The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Abstract: In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular < the number of inputs of the test unit (3) that are contained in the base of a cone (5).

Abstract: A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.

Abstract: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked out of the testing interface and to the DUT according to the test clock signal. Further, the test clock signal is delayed by a period of time and then a delayed clock signal is issued to the device. The data previously written to the DUT is read out of the DUT and compared with the test data received from the external test apparatus. The period of time by which the test clock signal is delayed can be varied to achieve a desired timing.

Abstract: A diffractive optical element contains a multiplicity of binary blazed diffraction structures, which substantially extend mutually parallel in a longitudinal direction. Perpendicularly to the longitudinal direction, the diffraction structures have a width g which is greater than the effective wavelength of electromagnetic radiation for which the diffractive optical element is designed. The diffraction structures respectively comprise a series of individual substructures, which produce a blaze effect and have a maximum extent p in the longitudinal direction which is less than the effective wavelength of the electromagnetic radiation, at least on average over a diffraction structure. In a plan view, the individual substructures respectively have the shape of a closed geometrical surface, which has an extent parallel to the longitudinal direction that varies perpendicularly to the longitudinal direction.

Abstract: Unidirectional input switching arrangements or pad circuits are supplemented by transfer switching devices employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple it to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which for its part can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.

Abstract: A method described is distinguished by the fact that an external test device brings about the execution, in a program-controlled unit, of a program that initiates, performs or supports the testing of the program-controlled unit. As a result, program-controlled units can be rapidly and reliably tested under all circumstances with minimal outlay.

Abstract: A method described is distinguished by the fact that an external test device brings about the execution, in a program-controlled unit, of a program that initiates, performs or supports the testing of the program-controlled unit. As a result, program-controlled units can be rapidly and reliably tested under all circumstances with minimal outlay.

Abstract: The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Abstract: A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subunit being required for executing a respective command, selecting, if available, a subunit of the given type of subunit, configuring configurable connections provided around the subunit selected in the selecting step, if the subunit of the given type of subunit is found in the selecting step, and ascertaining configuration data with the step of implementing the commands and/or command sequences. The configurable hardware block is configured by using the configuration data.

Abstract: An apparatus for cutting tubes has at least one cutting tool that contacts an anvil of a counterstay. The anvil is arranged relative to a cutting point of the cutting tool within the interior of a tube. The cutting tool can be fed in towards the counterstay during the cutting operation and can be limited in its cutting movement by the counterstay at the end of the cutting operation. The anvil is arranged in a yielding manner in the counterstay in the infeed direction of the cutting tool.