Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.

Abstract: The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.

Abstract: The invention relates to a polymer transistor arrangement, an integrated circuit arrangement and a method for producing a polymer transistor arrangement. The polymer transistor arrangement contains a polymer transistor formed in and/or on a substrate. The polymer transistor contains a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, a gate region and a gate-insulating layer between channel region and gate region. A drive circuit of the polymer transistor arrangement is set up in such a way that it provides the source/drain regions and the gate region with electrical potentials such that the junction between at least one of the source/drain regions and the channel region can be operated as a diode.

Abstract: A transistor arrangement having a multiplicity of transistors interconnected with one another, having a noise detection device, which is set up for detecting the 1/f noise of at least one portion of the transistors, having a selection device, which is set up for selecting at least one of the transistors, on the basis of the ascertained 1/f noise characteristic of the transistors, in the case of which the 1/f noise is sufficiently low.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.

Abstract: A force sensor based on an organic field effect transistor applied on a substrate is disclosed. In one embodiment, a mechanical force acting on the transistor causes a change in its source-drain voltage or its source-drain current which corresponds to said force and which can in each case be detected as measurement quantity for the acting force, a diaphragm-based pressure sensor that uses a force sensor of this type, a one- or two-dimensional position sensor that uses a multiplicity of force sensors of this type, and a fingerprint sensor that uses a multiplicity of such force sensors.

Abstract: One aspect of the invention relates to a rectifier circuit for providing a rectified voltage, with a first AC voltage terminal to which an AC voltage can be applied, with a first DC voltage terminal to which a DC voltage can be provided, and with a control switching element between the first AC voltage terminal and the first DC voltage terminal. The control switching element only couples the first AC voltage terminal to the first DC voltage terminal if the electrical potential at the first AC voltage terminal has a predeterminable polarity compared with a reference potential and if the amount of the electrical potential at the first DC voltage terminal is less than or equal to the amount of the electrical potential at the first AC voltage terminal.

Abstract: The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.

Abstract: Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected by the RTS detection unit and thus generates a digitized RTS, a signal state duration detection unit that determines, from the digitized RTS, a first time variable representing the time duration of at least one first signal state of the generated RTS and a second time variable representing the time duration of at least one second signal state of the generated RTS, and a random number conversion unit, which is coupled to the signal state duration detection unit, and that generates a random number from the first time variable and the second time variable.

Abstract: A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted.

Abstract: A biochemical semiconductor chip laboratory is disclosed including a coupled address and control chip for biochemical analyses and a method for producing the same. In at least one embodiment the semiconductor chip laboratory has a semiconductor sensor chip, which provides numerous analytical positions for biochemical samples in a matrix. The sensor chip is located on the address and control chip and the analytical positions are in electric contact with a printed contact structure on the upper face of the address and control chip via low-resistance through-platings through the semiconductor substrate of the semiconductor chip.

Abstract: A micromechanical sensor element for recording the bonding of molecules to the micromechanical sensor element. The sensor element having a substrate and at least one electrical terminal. There is also an oscillatable element that is coupled to the electrical terminal in such a manner that an electrical variable that characterizes the oscillation behavior of the oscillatable element may be provided at the electrical terminal. Further, there is a molecule coupling layer, arranged in such a manner that molecules may bond to the molecule coupling layer. The molecule coupling layer is coupled to the oscillatable element in such a manner that bonding of molecules to the molecule coupling layer causes a change in the oscillation behavior of the oscillation element.

Abstract: In an embodiment of the invention, a CMOS circuit arrangement is provided. The CMOS circuit arrangement includes a PMOS logic circuit providing a logic function, having PMOS field effect transistors, wherein a first operating potential is fed to an input of a PMOS logic circuit, an NMOS logic circuit providing the logic function, having NMOS field effect transistors, a first clock transistor, the first source/drain terminal of which is coupled to an input of the NMOS logic circuit, wherein a clock signal is applied to the gate terminal of the first clock transistor, and wherein a second operating potential is fed to the second source/drain terminal. An output of the PMOS logic circuit and an output of the NMOS logic circuit are coupled to one another. Furthermore, an inverter circuit is coupled to the output of the PMOS logic circuit and to the output of the NMOS logic circuit.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.

Abstract: An amplifier circuit for an oscillator in a defined oscillating frequency range includes a plurality of transconductors, wherein at least one transconductor has a positive transconductance, and wherein at least one other transconductor has a negative transconductance, wherein the transconductors together provide a positive amplification, and a passive impedance element coupled to at least one fed back transconductor, wherein the transconductance of the transconductor and the impedance element are dimensioned so that, in the oscillating frequency range, a given phase difference is present between a signal at the input and a signal at the output.

Abstract: An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: An identification data carrier has a substrate as well as a resonant circuit structure, which is formed on or in the substrate, for an electromagnetic resonant circuit. The resonant circuit structure has a resonant frequency which is specific for an object to be identified. A read apparatus for reading object-specific information which is contained in an identification data carrier has, an electromagnetic radiation source for emission of electromagnetic energy in a predeterminable frequency range, a detection device for detection of the electromagnetic energy which is absorbed by a resonant circuit structure of the identification data carrier at different frequencies in the frequency range, and for determination of the value of the resonant frequency of the resonant circuit structure, a determination device for determination of the object-specific information which is contained in the identification data carrier, from the value of the resonant frequency of the resonant circuit structure.

Abstract: A clock transistor and a second operating potential functioning as a circuit breaker, are mounted between the outlet of an NMOS logic circuit.