Patents by Inventor Ralf Illgen
Ralf Illgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9012277Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.Type: GrantFiled: January 9, 2012Date of Patent: April 21, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen
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Patent number: 8941187Abstract: In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.Type: GrantFiled: January 13, 2012Date of Patent: January 27, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Patent number: 8916928Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.Type: GrantFiled: September 27, 2013Date of Patent: December 23, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Patent number: 8912606Abstract: Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.Type: GrantFiled: April 24, 2012Date of Patent: December 16, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Publication number: 20140361335Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: Stefan Flachowsky, Ralf Illgen, Gerd Zschaezsch
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Patent number: 8835936Abstract: A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.Type: GrantFiled: November 15, 2012Date of Patent: September 16, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Stefan Flachowsky, Ralf Illgen
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Patent number: 8835255Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.Type: GrantFiled: January 23, 2013Date of Patent: September 16, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Stefan Flachowsky, Tom Hermann, Ralf Illgen
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Publication number: 20140246696Abstract: When forming sophisticated semiconductor devices including N-channel transistors with strain-inducing embedded source and drain semiconductor regions, N-channel transistor performance may be enhanced by selectively growing embedded pure silicon source and drain regions in cavities exposing the silicon/germanium layer of a Si/SiGe-substrate, wherein the silicon layer of the Si/SiGe-substrate may exhibit a strong bi-axial tensile strain. The bi-axial tensile strain may improve both electron and hole mobility.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Roman Boschke, Ralf Illgen
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Publication number: 20140206157Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.Type: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Stefan Flachowsky, Tom Herrmann, Ralf Illgen
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Patent number: 8753969Abstract: A MOS device and methods for its fabrication are provided. In one embodiment the MOS device is fabricated on and within a semiconductor substrate. The method includes forming a gate structure having a top and sidewalls and having a gate insulator overlying the semiconductor substrate, a gate electrode overlying the gate insulator, and a cap overlying the gate electrode. An oxide liner is deposited over the top and sidewalls of the gate structure. In the method, the cap is etched from the gate structure and oxide needles extending upward from the gate structure are exposed. A stress-inducing layer is deposited over the oxide needles and gate structure and the semiconductor substrate is annealed. Then, the stress-inducing liner is removed.Type: GrantFiled: January 27, 2012Date of Patent: June 17, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Stefan Flachowsky, Ralf Illgen
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Publication number: 20140131735Abstract: A method comprises providing a semiconductor structure comprising a substrate, an electrically insulating layer on the substrate and a semiconductor feature on the electrically insulating layer. A gate structure is formed on the semiconductor feature. An in situ doped semiconductor material is deposited on portions of the semiconductor feature adjacent the gate structure. Dopant is diffused from the in situ doped semiconductor material into the portions of the semiconductor feature adjacent the gate structure, the diffusion of the dopant into the portions of the semiconductor feature adjacent the gate structure forming doped source and drain regions in the semiconductor feature.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Jan Hoentschel, Stefan Flachowsky, Ralf Illgen
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Publication number: 20140117418Abstract: Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
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Patent number: 8647951Abstract: Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.Type: GrantFiled: August 24, 2011Date of Patent: February 11, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
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Publication number: 20140027825Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.Type: ApplicationFiled: September 27, 2013Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Publication number: 20140030876Abstract: A method for fabricating an integrated circuit having a FinFET structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures. The method further includes removing the silicon oxide formed over the condensed fin structures so as to expose the condensed fin structures.Type: ApplicationFiled: July 27, 2012Publication date: January 30, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Stefan Flachowsky, Ralf Illgen
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Publication number: 20140015055Abstract: A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
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Publication number: 20130341722Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) substrate. A PFET temporary gate structure and an NFET temporary gate structure are formed on the substrate. The method implants ions to form lightly doped active areas around the gate structures. A diffusionless annealing process is performed on the active areas. Further, a compressive strain region is formed around the PFET gate structure and a tensile strain region is formed around the NFET gate structure.Type: ApplicationFiled: June 22, 2012Publication date: December 26, 2013Applicant: GLOBALFOUNDRIES Inc.Inventors: Ralf Illgen, Stefan Flachowsky
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Patent number: 8580643Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.Type: GrantFiled: August 24, 2011Date of Patent: November 12, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: Tim Baldauf, Andy Wei, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Publication number: 20130277746Abstract: Methods for forming integrated circuits and integrated circuits are disclosed. The integrated circuits comprise gate structures overlying and transverse to one or more fins that are delineated by trenches formed in a semiconductor substrate. Protruding portions are formed in the trenches in between the gate electrode structure on exposed sidewall surfaces of the one or more fins. The trenches are filled with an insulating material between the protruding portions and the gate structures.Type: ApplicationFiled: April 24, 2012Publication date: October 24, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Tim Baldauf, Tom Herrmann, Stefan Flachowsky, Ralf Illgen
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Publication number: 20130244437Abstract: One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Stefan Flachowsky, Ralf Illgen, Thilo Scheiper