Abstract: An integrated device comprises an electrically conductive substrate having an upper surface comprising a recess and a lower surface for contacting the device, a multi-layer stack provided on the upper surface of the substrate and lining the recess, and an electrically conductive layer for contacting the device provided on the multi-layer stack. The multi-layer stack comprises a first, a second, a third and a fourth dielectric layer. Immediately adjacent dielectric layers have different bandgaps to trap charge carriers at respective interfaces between the dielectric layers during operation of the device.

Abstract: A carrier substrate for semiconductor structures which can be transferred by transfer printing, and manufacture of the semiconductor structures on the carrier substrate. The number of the required process steps and thus the required effort is to be generally reduced in the manufacture of component structures on a carrier substrate for providing the component structures in a state in which they can be transferred to a further substrate by transfer printing. For this purpose, it is suggested to produce semiconductor structures to be transferred on a carrier substrate. The method comprises providing a carrier substrate (10) including a semiconductor material with a selected crystal orientation. An active region (11) is produced which has an exposed semiconductor surface (11) and is almost completely delimited by dielectric regions (30, 80) including an isolating dielectric material.

Abstract: The invention involves a semiconductor wafer for a (micro) transfer printing process and the manufacture of such a wafer to enable a (micro) transfer printing process with increased adhesion of the semiconductor element (20) transferred or printed on a surface of a carrier substrate. This is achieved with the semiconductor wafer (2), which consists of one layer (31, 31?, 31?, 31*) with at least one functional frame (34, 34?, 34?, 34*). Located within this (34, 36a) is a bonding material (36, 39; 54, 55). The bonding material (36) within the functional frame (34, 36a) has an at least partially concave surface (38, 38?, 38?) for contacting an underside (22) of a printed or transferred semiconductor element (20, 40).

Abstract: A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10?) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14?, 14?); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

Abstract: A unit trench capacitor in a substrate includes one or more trenches in the substrate, a dielectric layer, a first electrode and a second electrode. Walls of the one or more trenches are covered by the dielectric layer which separates the first electrode from the second electrode. Each trench follows a closed curve. The closed curve of each trench has one or more elongated parts in directions in which the substrate has a maximum elastic modulus, or the closed curve of each trench has a circular shape if the substrate has an isotropic elastic modulus.

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: A semiconductor component includes at least two functional units which are identical to one another and are wired to one another, the identical functional units each include at least one gate finger, at least one source finger and at least one drain finger; the wiring comprising conductor tracks. A first track connects the gate fingers respectively, a second track connects the source fingers respectively, and a third track connects the drain fingers of the at least two same functional units, respectively.

Abstract: A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10?) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14?, 14?); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

Abstract: Methods for mounting devices on a non-native substrate by a transfer stamp are disclosed. A method may include providing (102) a first semiconductor wafer (300) comprising mostly functional first devices (304) and a few non-functional first devices (302) in a first grid pattern (x, y); providing (102) a second semiconductor wafer (400) comprising second devices (402) in a second grid pattern (x?, y?); removing (108) the non-functional first devices (302) from the first semiconductor wafer (300) in respective individual first transfer printing steps; transferring (110) a plurality of the functional first devices (304) from the first semiconductor wafer (300) to the associated second devices (402) of the second semiconductor wafer (400) in a second transfer printing step; and transferring (112) individual functional first devices (304) of the first semiconductor wafer (300) to second devices not having first devices printed thereon (408) in respective individual third transfer printing steps.

Abstract: A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10?) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14?, 14?); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

Abstract: The present invention suggests a semiconductor device for integration into a power module. The semiconductor device comprises (a) a semiconductor layer (10), a first side of the semiconductor layer (10) having a plurality of depressions (11); (b) an insulating layer (12; 12a, 12b), the insulating layer being deposited on the first side of the semiconductor layer (10) and engaging in the depressions (11); (c) a first electrically conductive layer (14; 14a, 14b) for contacting the semiconductor device (1, 2), the first electrically conductive layer (14; 14a, 14b) being deposited on the insulating layer (12a, 12b); and (d) a second electrically conductive layer (16) for contacting the semiconductor device (1, 2), the second electrically conductive layer (16) being deposited on a second side of the semiconductor layer (10) opposite to the first side.

Abstract: The transfer of devices or device components from a carrier substrate to a further carrier substrate or to a plurality of further carrier substrates can be performed with little effort (few transfer steps) to the at least one further carrier substrate. The method comprises producing first devices on the first carrier substrate in a two-dimensional grid. It comprises defining positions on the second carrier substrate on the basis of the two-dimensional grid for at least some of the first devices. It comprises releasing a plurality of the first devices from the first carrier substrate while maintaining the two-dimensional grid. Finally, the plurality of first devices are applied to the second carrier substrate in the defined positions while maintaining the two-dimensional grid or a multiple thereof in at least one of the two directions.

Abstract: A semiconductor component is to be manufactured in a more time- and cost-efficient manner. The flexibility of the manufacturing process for the production of the semiconductor device is to be increased. This can be achieved with a semiconductor component (50), including a at least two functional units (2) which are identical to one another and are wired to one another, the identical functional units (2) each comprising at least one gate finger (16), at least one source finger (17) and at least one drain finger (18); the wiring comprising conductor tracks. A first track (26) connects the gate fingers (16) respectively, a second track (27) connects the source fingers (17) respectively, and a third track (28) connects the drain fingers (18) of the at least two same functional units (2) respectively.

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: A method for producing a semiconductor substrate and a semiconductor substrate for use in epitaxial methods of a semiconductor material are described. The semiconductor substrate includes a support slice, an intermediate layer situated on the support slice, and an active layer situated on the intermediate layer. The intermediate layer includes a material which has a reduced viscosity or flows when the semiconductor substrate is used in an epitaxial method in order to enable at least a partial adaptation of a crystal lattice of the active layer to a crystal lattice of the semiconductor material at the transition between the active layer and the semiconductor material.

Abstract: Methods for mounting devices on a non-native substrate by a transfer stamp are disclosed. A method may include providing (102) a first semiconductor wafer (300) comprising mostly functional first devices (304) and a few non-functional first devices (302) in a first grid pattern (x, y); providing (102) a second semiconductor wafer (400) comprising second devices (402) in a second grid pattern (x?, y?); removing (108) the non-functional first devices (302) from the first semiconductor wafer (300) in respective individual first transfer printing steps; transferring (110) a plurality of the functional first devices (304) from the first semiconductor wafer (300) to the associated second devices (402) of the second semiconductor wafer (400) in a second transfer printing step; and transferring (112) individual functional first devices (304) of the first semiconductor wafer (300) to second devices not having first devices printed thereon (408) in respective individual third transfer printing steps.

Abstract: A semiconductor device may include a first active component region (20) and a second active region (22) extending flat along a first lateral direction (L1) and a second lateral direction (L2) deviating from said first lateral direction. The semiconductor device may include a trench isolation structure (10, 10?) that electrically isolates the first active component region (20) from the second active region (22) along the first lateral direction (L1) and comprises at least one electrically conductive sidewall (14, 14?, 14?); said trench isolation structure (10) having a continuously extending insulating trench isolation base wall (30) and a plurality of spaced apart trench isolation portions (32a, 32b) with electrically conductive sidewall portions (14a, 14b) therebetween. The plurality of trench isolation portions (32a, 32b) and the electrically conductive sidewall portions (14a, 14b) are spaced (a, b) from the base wall (30).

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: A component to be transferred to a receiving substrate is to be coupled both electrically and thermally. This is achieved by an integrated circuit comprising a substrate and a plurality of first components formed in or on the substrate. A plurality of metallization layers are provided. A second component applied by transfer printing is provided which is positioned, at least in part, on a level with and laterally adjacent to at least one of the plurality of metallization layers.

Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.