Abstract: The invention relates to a geometric design and corresponding methods for components 22, which are produced on a carrier substrate 10 and prepared by detachment in an etching process 30 for a subsequent absorption and a transfer with a stamp for application to a further substrate. The components 22 are designed in such a way that additional active surfaces are provided for the etching process 30 for undercut the components, so that a faster, more reliable and more homogeneous etching profile is achieved.

Abstract: A method for producing a semiconductor substrate and a semiconductor substrate for use in epitaxial methods of a semiconductor material are described. The semiconductor substrate includes a support slice, an intermediate layer situated on the support slice, and an active layer situated on the intermediate layer. The intermediate layer includes a material which has a reduced viscosity or flows when the semiconductor substrate is used in an epitaxial method in order to enable at least a partial adaptation of a crystal lattice of the active layer to a crystal lattice of the semiconductor material at the transition between the active layer and the semiconductor material.

Abstract: A carrier substrate for semiconductor structures which can be transferred by transfer printing, and manufacture of the semiconductor structures on the carrier substrate. The number of the required process steps and thus the required effort is to be generally reduced in the manufacture of component structures on a carrier substrate for providing the component structures in a state in which they can be transferred to a further substrate by transfer printing. For this purpose, it is suggested to produce semiconductor structures to be transferred on a carrier substrate. The method comprises providing a carrier substrate (10) including a semiconductor material with a selected crystal orientation. An active region (11) is produced which has an exposed semiconductor surface (11) and is almost completely delimited by dielectric regions (30, 80) including an isolating dielectric material.

Abstract: The transfer of devices or device components from a carrier substrate to a further carrier substrate or to a plurality of further carrier substrates can be performed with little effort (few transfer steps) to the at least one further carrier substrate. The method comprises producing first devices on the first carrier substrate in a two-dimensional grid. It comprises defining positions on the second carrier substrate on the basis of the two-dimensional grid for at least some of the first devices. It comprises releasing a plurality of the first devices from the first carrier substrate while maintaining the two-dimensional grid. Finally, the plurality of first devices are applied to the second carrier substrate in the defined positions while maintaining the two-dimensional grid or a multiple thereof in at least one of the two directions.

Abstract: Individual coils as well as two or more coils arranged one over the other or one coil in combination with a sensor, which can be integrated into planar semiconductor technology are described. A coil comprises a turn and two supply lines for supplying current to the coil. The turn and the supply lines are formed from a metal layer. One of the two supply lines is connected to a first end of the turn and the other of the two supply lines is connected to a second end of the turn.

Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.

Abstract: The power transistor configured to be integrated into a trench-isolated thick layer SOI-technology with an active silicon layer with a thickness of about 50 ?m. The power transistor may have a lower resistance than the DMOS transistor and a faster switch-off behavior than the IGBT.

Abstract: It is the purpose of the invention to provide a MOS transistor (20) which guarantees a voltage as high as possible, has a required area as small as possible and which enables the integration into integrated smart power circuits. It results there from as an object of the invention to form the edge structure of the transistors such that it certainly fulfils the requirements on high breakthrough voltages, a good isolation to the surrounding region and requires a minimum of surface on the silicon disc anyway. This is achieved with an elongated MOS power transistor having drain (30) and source (28) for high rated voltages above 100V, wherein the transistor comprises an isolating trench (22) in the edge area for preventing an early electrical breakthrough below the rated voltage. The trench is lined with an isolating material (70, 72), wherein the isolating trench terminates the circuit component.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches (28, 43, 70) produced by etching within certain regions (38, 39), which are electrically insulated from each other, of the active semiconductor layer (24, 42) by means of a cover layer or cover layers (29) using MOCVD methods.

Abstract: The invention describes a method for fabricating silicon semiconductor wafers with the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafers are used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Abstract: The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.

Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.

Abstract: The invention relates to a method for producing silicon semiconductor wafers and components having layer structures of III-V layers for integrating III-V semiconductor components. The method employs SOI silicon semiconductor wafers having varying substrate orientations, and the III-V semiconductor layers are produced in trenches (28, 43, 70) produced by etching within certain regions (38, 39), which are electrically insulated from each other, of the active semiconductor layer (24, 42) by means of a cover layer or cover layers (29) using MOCVD methods.

Abstract: A description is given of a method for producing isolation trenches (32, 34) with different sidewall dopings on a silicon-based substrate wafer for use in the trench-isolated smart power technology. In this case, a first trench (32) having a first width and a second trench (34) having a second width which is greater than the first width are formed using a hard mask (30). The sidewalls of the first and second trenches are doped in accordance with a first doping type in order to produce sidewalls having a first doping. A material layer (50, 51, 60, 61) is deposited with a thickness determined so as to fill the first trench (32) completely up to and beyond the hard mask and to maintain the gap (34a) in the second trench (34). By means of isotropic etching the material layer is removed from the second trench, but residual material of the material layer is maintained in the first trench.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: The invention describes a method for fabricating silicon semiconductor waferswith the layer structures from III-V semiconductor layers for the integration of HEMTs based on semiconductor III-V layers with silicon components. SOI silicon semiconductor wafersare used, the active semiconductor layer of which has the III-V semiconductor layers (24) of the HEMT design (2) placed on it stretching over two mutually insulated regions (24a, 24b) of the active silicon layer. An appropriate layer arrangement is likewise disclosed.

Abstract: Disclosed is a semiconductor structure for producing a handle wafer contact in trench insulated SOI discs which may be used as a deep contact (7, 6, 30?) to the handle wafer (1) of a thick SOI disc as well as for a trench insulation (40). Therein, the same method steps are used for both structures which are used as deep contact to the handle wafer of the thick SOI disc as well as trench insulation.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.