Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.

Abstract: There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.

Abstract: A multiple application smart card uses hardware firewalls and an internal communications scheme to isolate applications from different service providers. A first application from a first service provider is stored within a first supplemental security domain of a memory device on the multiple application smart card. A second application from a second service provider is stored within a second SSD of the memory device. A hardware firewall is located between the first and second applications of the first and second SSDs. The hardware firewall prevents direct data access between the first and second applications of the first and second SSDs.

Abstract: A system and method for obtaining an authorization key to use a product utilizes a secured product identification code, which includes a serial number and at least one code that is generated based on a cryptographic algorithm.

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract: A flip-flop (10) is disclosed comprising a slave latch (30) and a master latch (20). Each of the slave and master latch comprise a pair of cross-coupled logic gates (21, 22, 31, 32). A cross coupling connection of the slave or master latch (30, 20) comprises a resistive element (8, 9, 11, 12) arranged to reduce the sensitivity of the flip-flop (10) to a current injection.

Abstract: A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.

Abstract: A multiple application smart card uses hardware firewalls and an internal communications scheme to isolate applications from different service providers. A first application from a first service provider is stored within a first supplemental security domain of a memory device on the multiple application smart card. A second application from a second service provider is stored within a second SSD of the memory device. A hardware firewall is located between the first and second applications of the first and second SSDs. The hardware firewall prevents direct data access between the first and second applications of the first and second SSDs.

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract: A multiple application smart card (102) uses hardware firewalls (130) and an internal communications scheme to isolate applications from different service providers. A first application (116) from a first service provider is stored within a first supplemental security domain (SSD) (126) of a memory device on the multiple application smart card (102). A second application (116) from a second service provider is stored within a second SSD (128) of the memory device. A hardware firewall (130) is located between the first and second applications (116) of the first and second SSDs (128). The hardware firewall (130) prevents direct data access between the first and second applications (116) of the first and second SSDs (128).

Abstract: A system and method for obtaining an authorization key to use a product utilizes a secured product identification code, which includes a serial number and at least one code that is generated based on a cryptographic algorithm.

Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.

Abstract: A system and method for obtaining an authorization key to use a product utilizes a secured product identification code, which includes a serial number and at least one code that is generated based on a cryptographic algorithm.

Abstract: An integrated circuit 100 is provided, which is configured for authentication itself and technical information concerning the integrated circuit or its installed software to an external computing device 200. The integrated circuit 100 comprises a signer 130 for producing a signature over the information and a challenge using a cryptographic signing key, and a communication module 110 for providing the information and the signature to the computing device 200. In response to receiving the information and the authentication, the computing device 200 may install new application code on the integrated circuit. After the installation, the integrated circuit may authenticate information concerning the new application code to other computing devices. The integrated circuit is advantageously a multiple application smart card, since it allows application providers to obtain trust in the multiple application smart card without having a relationship with its manufacturer.

Abstract: A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M200) dispatching a first read request; (M400) dispatching a second read request; (M600) dispatching a further first read request; and (M1000-a) producing an anomaly signal if a first result produced by the memory in response to the first read request does not agree with a further first result produced by the memory in response to the further first read request.

Abstract: A multiple application smart card (102) uses hardware firewalls (130) and an internal communications scheme to isolate applications from different service providers. A first application (116) from a first service provider is stored within a first supplemental security domain (SSD) (126) of a memory device on the multiple application smart card (102). A second application (116) from a second service provider is stored within a second SSD (128) of the memory device. A hardware firewall (130) is located between the first and second applications (116) of the first and second SSDs (128). The hardware firewall (130) prevents direct data access between the first and second applications (116) of the first and second SSDs (128).

Abstract: A Microprocessor (1) in a security-sensitive computing system for processing an operand according to an instruction is for improving its security provided with a modulo-based check hardware (2) to perform operations in parallel to the microprocessor (1) and for comparing both results regarding congruence.