Abstract: An integrated circuit 100 is provided, which is configured for authentication itself and technical information concerning the integrated circuit or its installed software to an external computing device 200. The integrated circuit 100 comprises a signer 130 for producing a signature over the information and a challenge using a cryptographic signing key, and a communication module 110 for providing the information and the signature to the computing device 200. In response to receiving the information and the authentication, the computing device 200 may install new application code on the integrated circuit. After the installation, the integrated circuit may authenticate information concerning the new application code to other computing devices. The integrated circuit is advantageously a multiple application smart card, since it allows application providers to obtain trust in the multiple application smart card without having a relationship with its manufacturer.

Abstract: A system and method for obtaining an authorization key to use a product utilizes a secured product identification code, which includes a serial number and at least one code that is generated based on a cryptographic algorithm.

Abstract: A method for secure data reading and a data handling system is provided. The method protects the data reading from fault attacks by repeating read request in an interleaved manner, in particular the method comprises the steps of (M200) dispatching a first read request; (M400) dispatching a second read request; (M600) dispatching a further first read request; and (M1000-a) producing an anomaly signal if a first result produced by the memory in response to the first read request does not agree with a further first result produced by the memory in response to the further first read request.

Abstract: A method for the improvement of the security of microprocessors (1) with a cache memory (3, 4), whereas with a cache-instruction data can be written into the cache memory (3, 4), is improved to enhance the security of a system by inhibiting the direct writing of the cache-instruction into the cache memory (3, 4).

Abstract: A Microprocessor (1) in a security-sensitive computing system for processing an operand according to an instruction is for improving its security provided with a modulo-based check hardware (2) to perform operations in parallel to the microprocessor (1) and for comparing both results regarding congruence.

Abstract: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.

Abstract: The invention relates to a bus system for transmitting data between a processing unit (10) and a memory unit (19) comprising memory cells (17), in which a plurality of logic addresses is available for each memory cell (17). Dependent on the kind of address used, the data transmitted through the data bus (13) are differently manipulated by a data modification unit (16) so that, for protection against abuse of data, the unchanged identical data are not present at the data bus (13).

Abstract: In order to further develop a data processing device (100; 100?) having at least one microprocessor (90) and having at least one additional arithmetic unit (40) as well as a method of performing at least one particular defined calculation by means of the data processing device (100; 100?) in such a way that a plurality of calculations may be performed in sequence without any intervention by the microprocessor (90), it is proposed that the registers be loadable from at least one in particular peripheral memory (10), for example from at least one R[andom]A[ccess]M[emory], from at least one R[ead]O[nly]M[emory] or from at least one E[lectrically] E[rasable] P[rogrammable] R[ead]O[nly]M[emory.

Abstract: A data carrier is disclosed. The data carrier includes a data processing unit and at least one contactless interface via which the data processing unit can be coupled to a read/write apparatus in order to exchange data signals and to take up electrical energy for the operation of the data processing unit; the data processing unit is constructed at least mainly while using at least substantially asynchronously operating logic components (asynchronous logic). The data carrier according to the invention, such as a chip card, makes optimum use of the energy applied thereto and is at the same time protected against the tapping of the signal processing steps to be executed therein.

Abstract: The invention relates to a method and an arrangement for protecting digital parts of circuits, which method and arrangement may be used in particular to protect memory units in such digital circuits, and particularly in smart-card controllers, that contain secret data, against attacks in which the approach adopted is to change digital parts of circuits, and particularly the digital part of a smart-card controller, to an undefined state by brief voltage drops, e.g. by light-flash attacks.

Abstract: The invention relates to a circuit arrangement which includes a stage for the processing of data signals which are applied to the stage in a selectable sequence during time intervals defined by a clock signal. In order to construct a circuit arrangement of this kind in such a manner that the power consumption which is dependent on the data signals is disguised, the invention proposes to supply the circuit arrangement, with modified data signals, instead of the data signals to be processed, in a respective part of each time interval.

Abstract: The invention relates to a bus system for transmitting data between a processing unit (10) and a memory unit (19) comprising memory cells (17), in which a plurality of logic addresses is available for each memory cell (17). Dependent on the kind of address used, the data transmitted through the data bus (13) are differently manipulated by a data modification unit (16) so that, for protection against abuse of data, the unchanged identical data are not present at the data bus (13).

Abstract: In order to enable calculation of the square of a number comprising many digits by means of an arithmetic circuit which is arranged for the parallel processing of numbers having a substantially smaller number of digits, the number to be squared is subdivided into sub-numbers having a number of digits which is compatible with the arithmetic circuit, the individual sub-numbers being successively processed. For faster processing in the case of squaring operations, the multiplier circuit provided in the arithmetic circuit includes a position shift circuit capable of performing a shift of one position to the left in the case of multiplication of given pairs of sub-numbers, which shift corresponds to a multiplication by the factor 2. As a result, squaring can be performed while using fewer technical means. A method operating on the basis thereof so as to form the square of a large number modulo another large number is also disclosed.

Abstract: The arithmetic unit in a data processing system with a microprocessor and an additional arithmetic unit carries out special arithmetic operations, preferably integrated in a single semiconductor chip, is controlled by the microprocessor via a number of registers. Several sets of such registers are provided. The registers of one set are selected via a selection circuit. As a result, a set of registers which is not required during execution of a calculation by the arithmetic unit can be filled with new data by the microprocessor and, after completion of the calculation in the arithmetic unit, switching over to a newly filled set of registers takes place so that the arithmetic unit can continue with a new set of operands without having to observe a waiting period.