Patents by Inventor Ralf Otremba
Ralf Otremba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984392Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.Type: GrantFiled: August 27, 2021Date of Patent: May 14, 2024Assignee: Infineon Technologies AGInventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
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Patent number: 11978693Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.Type: GrantFiled: July 29, 2021Date of Patent: May 7, 2024Assignee: Infineon Technologies AGInventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
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Patent number: 11942383Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.Type: GrantFiled: October 14, 2021Date of Patent: March 26, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
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Publication number: 20240096842Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Publication number: 20240087995Abstract: A power semiconductor package includes: a die carrier having first and second opposite sides; and first and second power semiconductor dies each having first and second power electrodes on opposite sides. The second power electrodes face and are electrically coupled to the first side of the carrier. A molded body at least partially encapsulates the dies and has a first and second opposite sides and lateral sides connecting the first and second sides. First and second power contacts and first and second control contacts are arranged laterally next to each other. The first power electrode of the first die is electrically coupled to the first power contact by a first electrical connector. The first power electrode of the second die is electrically coupled to the second power contact by a second electrical connector. A width of each power contact is at least four times the width of each control contact.Type: ApplicationFiled: August 22, 2023Publication date: March 14, 2024Inventors: Ralf Otremba, Thai Kee Gan, Teck Sim Lee, Chwee Pang Tommy Khoo, Christian Schiele, Katrin Unterhofer, Patrick Uredat
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Patent number: 11929298Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.Type: GrantFiled: November 13, 2020Date of Patent: March 12, 2024Assignee: Infineon Technologies AGInventors: Jo Ean Joanna Chye, Edward Fuergut, Ralf Otremba
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Patent number: 11923276Abstract: A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.Type: GrantFiled: February 15, 2023Date of Patent: March 5, 2024Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Klaus Schiess, Michael Treu
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Patent number: 11915999Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.Type: GrantFiled: January 31, 2023Date of Patent: February 27, 2024Assignee: Infineon Technologies AGInventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
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Publication number: 20230402423Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.Type: ApplicationFiled: June 16, 2023Publication date: December 14, 2023Inventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber
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Patent number: 11804424Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: GrantFiled: December 1, 2020Date of Patent: October 31, 2023Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Publication number: 20230335530Abstract: A power device package includes first and second power transistor chips each having a control electrode, a first load electrode and a second load electrode. A control package terminal is electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection. A first package terminal is electrically coupled to the first load electrode of the first and second power transistor chips. A second package terminal is electrically coupled to the second load electrode of the first power transistor chip and/or the second power transistor chip. A length of the first wire bond connection is greater than a length of the second wire bond connection, and a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.Type: ApplicationFiled: April 4, 2023Publication date: October 19, 2023Inventor: Ralf Otremba
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Patent number: 11776882Abstract: A method includes: arranging a semiconductor device on a redistribution substrate, the device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, the redistribution substrate having an insulating board having a first major surface and a second major surface having solderable contact pads, so that the first power electrode is arranged on a first conductive pad and the control electrode is arranged on a second conductive pad on the first major surface; arranging a contact clip such that a web portion is arranged on the second power electrode and a peripheral rim portion is arranged on a third conductive pad on the first major surface; and electrically coupling the first power electrode, control electrode and peripheral rim portion to the respective conductive pads and electrically coupling the web portion to the second power electrode.Type: GrantFiled: April 4, 2022Date of Patent: October 3, 2023Assignee: Infineon Technologies Austria AGInventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
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Publication number: 20230298956Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove is formed in the first main surface, wherein the first groove is arranged between the first diepad and the second diepad, and a second groove is formed in the first main surface, wherein the second groove is arranged between the at least one lead and at least one of the first diepad and the second diepad.Type: ApplicationFiled: March 8, 2023Publication date: September 21, 2023Applicant: Infineon Technologies AGInventors: Chii Shang HONG, Li Fong CHONG, Yee Beng DARYL YEOW, Edward FÜRGUT, Mei Fen HIEW, Azlina KASSIM, Ralf OTREMBA, Bernd SCHMOELZER, Joon Shyan TAN, Lee Shuang WANG
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Publication number: 20230290709Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.Type: ApplicationFiled: May 16, 2023Publication date: September 14, 2023Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Publication number: 20230268255Abstract: A power semiconductor device includes: a package and a plurality of power semiconductor chips, each power semiconductor chip including a semiconductor body, a first load terminal, a second load terminal and a control terminal. The device also includes a plurality of outside terminals. The outside terminals include: one or more first outside terminals electrically connected with the first load terminals; one or more second outside terminals each of which is electrically connected with each of the second load terminals; and a plurality of third outside terminals. Each control terminal is electrically connected with at least one individual third outside terminal of the plurality of third outside terminals.Type: ApplicationFiled: February 17, 2023Publication date: August 24, 2023Inventors: Ralf Otremba, Christian Fachmann
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Patent number: 11715719Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.Type: GrantFiled: May 15, 2020Date of Patent: August 1, 2023Assignee: Infineon Technologies AGInventors: Edward Fuergut, Ralf Otremba, Irmgard Escher-Poeppel, Martin Gruber
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Publication number: 20230230903Abstract: A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.Type: ApplicationFiled: December 21, 2022Publication date: July 20, 2023Applicant: Infineon Technologies AGInventors: Hooi Boon TEOH, Hao ZHUANG, Oliver BLANK, Paul Armand CALO, Markus DINKEL, Josef Höglauer, Daniel Hölzl, Wee Aun JASON LIM, Gerhard Thomas Nöbauer, Ralf OTREMBA, Martin Pölzl, Ying Pok SAM, Xaver Schlögel, Chee Voon TAN
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Patent number: 11688670Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.Type: GrantFiled: October 26, 2020Date of Patent: June 27, 2023Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
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Publication number: 20230197582Abstract: A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Inventors: Ralf Otremba, Klaus Schiess, Michael Treu
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Publication number: 20230187326Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.Type: ApplicationFiled: January 31, 2023Publication date: June 15, 2023Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic