Patents by Inventor Ralf Otremba

Ralf Otremba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220149038
    Abstract: A semiconductor chip includes a semiconductor body having a main surface and a rear surface opposite the main surface, a first bond pad disposed on the main surface, a second bond pad disposed on the rear surface, a first switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the first bond pad, and a second switching device that is monolithically integrated in the semiconductor body and has a first input-output terminal that is electrically connected to the second bond pad.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 12, 2022
    Inventors: Edward Fuergut, Peter Friedrichs, Ralf Otremba, Hans-Joachim Schulze
  • Publication number: 20220148934
    Abstract: A package for mounting on a mounting base is disclosed. In one example, the package comprises a carrier, an electronic component mounted at the carrier, leads electrically coupled with the electronic component and to be electrically coupled with the mounting base, and a linear spacer for defining a spacing with respect to the carrier.
    Type: Application
    Filed: October 14, 2021
    Publication date: May 12, 2022
    Applicant: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Ralf Otremba, Daniel Pedone, Bernd Schmoelzer
  • Patent number: 11329000
    Abstract: A package includes: a package body having an outside housing including first and second package sides and package sidewalls that extend between the first and second package sides; first and second electrically conductive interface layers spaced apart from each other at the outside housing; and first and second power semiconductor chips arranged within the package body, both chips having a respective first load terminal and a respective second load terminal. The first load terminals are electrically connected to each other within the package body. The second load terminal of the first chip is electrically connected to the first electrically conductive interface layer. The second load terminal of the second chip is electrically connected to the second electrically conductive interface layer. The outside housing of the package body further includes a creepage structure having a minimum dimension between the first electrically conductive interface layer and the second electrically conductive interface layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 11302610
    Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
  • Publication number: 20220102263
    Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 31, 2022
    Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
  • Publication number: 20220102253
    Abstract: A semiconductor package includes: a leadframe having first, second and third die pads and leads, each die pad having upper and lower surfaces; first and second power semiconductor devices; a control semiconductor device; and a mold compound. The upper surface of each die pad is arranged within the mold compound. The lower surface of the second die pad is spaced apart from a side face of the semiconductor package by a distance that is greater than a length of the individual leads. The first power semiconductor device is mounted on the upper surface of the first die pad and electrically coupled to the second die pad by one or more first connectors extending between the first device and the upper surface of the second die pad. The upper surface of the second die pad is occupied by the one or more connectors or in direct contact with the mold compound.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 31, 2022
    Inventors: Thomas Beer, Daniel Hoelzl, Ralf Otremba, Klaus Schiess
  • Publication number: 20220093496
    Abstract: A semiconductor device forming a bidirectional switch includes first and second carriers, first and second semiconductor chips arranged on the first and second carriers, respectively, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor chips. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Ralf Otremba, Klaus Schiess, Michael Treu
  • Publication number: 20220037240
    Abstract: A semiconductor device package includes a printed circuit board including a first central area, a second lateral area, and a third lateral area, a semiconductor die including a first main face and a second main face opposite the first main face, a first contact pad on the first main face and a second contact pad on the second main face, the semiconductor die disposed in the first central area of the printed circuit board, a first metallic side wall of the semiconductor device package disposed in the second lateral area of the printed circuit board, a second metallic side wall of the semiconductor device package disposed in the third lateral area of the printed circuit board, wherein at least one of the first metallic side wall and the second metallic side wall is electrically connected with one of the first contact pad or the second contact pad.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Inventors: Petteri Palm, Ulrich Froehler, Ralf Otremba, Andreas Riegler
  • Patent number: 11217510
    Abstract: A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Michael Treu
  • Patent number: 11211304
    Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: December 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Guenther Lohmann, Bernd Schmoelzer, Fabian Schnoy
  • Publication number: 20210225795
    Abstract: A SiC power semiconductor device includes: a power semiconductor die including SiC and a metallization layer, wherein the metallization layer includes a first metal; a die carrier, wherein the power semiconductor die is arranged over the die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and a first intermetallic compound arranged between the power semiconductor die and the plating and including Ni3Sn4.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 22, 2021
    Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20210175157
    Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.
    Type: Application
    Filed: December 1, 2020
    Publication date: June 10, 2021
    Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
  • Publication number: 20210134708
    Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
    Type: Application
    Filed: October 26, 2020
    Publication date: May 6, 2021
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20210118843
    Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 22, 2021
    Applicant: Infineon Technologies AG
    Inventors: Edmund Riedl, Wu Hu Li, Alexander Heinrich, Ralf Otremba, Werner Reiss
  • Publication number: 20210074614
    Abstract: A package includes a package body with a package top side, package footprint side and package sidewalls extending from the package footprint side to the package top side; power semiconductor chips electrically connected in parallel and each having first and second load terminals and being configured to block a blocking voltage and conduct a chip load current between the load terminals; a lead frame structure configured to electrically and mechanically couple the package to a carrier with the package footprint side facing the carrier, the lead frame structure including first outside terminals extending out of the package body for interfacing with the carrier. Each first load terminal is electrically connected, at least by one package body internal connection member, to at least two of the first outside terminals. A horizontally extending conduction layer at the package top side or footprint side is electrically connected with each second load terminal.
    Type: Application
    Filed: September 4, 2020
    Publication date: March 11, 2021
    Inventors: Ralf Otremba, Teck Sim Lee, Lee Shuang Wang, Mohd Hasrul Zulkifli
  • Publication number: 20210035876
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body and a semiconductor component encapsulated in the package body. A cavity is formed in a bottom surface of the package body.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Markus Dinkel, Josef Hoeglauer, Angela Kessler
  • Publication number: 20210035945
    Abstract: An arrangement is disclosed. In one example, the arrangement of a conductor and an aluminum layer soldered together comprises a substrate and the aluminum layer disposed over the substrate. The aluminum forms a first bond metal. An intermetallic compound layer is disposed over the aluminum layer. A solder layer is disposed over the intermetallic compound layer, wherein the solder comprises a low melting majority component. The conductor is disposed over the solder layer, wherein the conductor has a soldering surface which comprises a second bond metal. The intermetallic compound comprises aluminum and the second bond metal and is predominantly free of the low melting majority component.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Applicant: Infineon Technologies AG
    Inventors: Alexander Heinrich, Ralf Otremba, Stefan Schwab
  • Patent number: 10903133
    Abstract: A package encloses a power semiconductor die and has a package body with a top side, footprint side and sidewalls. The die has first and second load terminals and blocks a blocking voltage between the load terminals. The package further includes: a lead frame structure for electrically and mechanically coupling the package to a support, the lead frame structure including an outside terminal extending out of the package footprint side and/or out of one of the package sidewalls and electrically connected with the first load terminal; and a top layer arranged at the package top side and electrically connected with the second load terminal. A heat spreader is mounted onto the top layer with a bottom surface facing the top layer. The area of the top surface of the heat spreader is greater than the area of the bottom surface.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Markus Dinkel, Ulrich Froehler, Josef Hoeglauer, Uwe Kirchner, Guenther Lohmann, Klaus Schiess, Xaver Schloegel
  • Publication number: 20210020539
    Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.
    Type: Application
    Filed: July 15, 2020
    Publication date: January 21, 2021
    Applicant: Infineon Technologies AG
    Inventors: Ralf Otremba, Teck Sim Lee, Klaus Schiess, Xaver Schloegel, Lee Shuang Wang, Mohd Hasrul Zulkifli
  • Patent number: 10896893
    Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Edmund Riedl, Wu Hu Li, Alexander Heinrich, Ralf Otremba, Werner Reiss