Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.

Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Abstract: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Abstract: A connection structure is provided that includes a semiconductor substrate, a first layer arranged on the semiconductor substrate, the first layer being configured to provide shielding against radioactive rays, a second layer arranged on the first layer, the second layer including solder including Pb, and an electrically conductive member arranged on the second layer.

Abstract: A package encloses a power semiconductor die that has a first load terminal at a die frontside facing a footprint side of the package and a second load terminal arranged at a die backside facing a top side of the package. The package also includes a lead frame configured to electrically and mechanically couple the package to a support. The lead frame has a planar first outside terminal electrically connected with the first load terminal and a planar second outside terminal electrically connected with the second load terminal, The planar first outside terminal is configured to interface with the support by means of a first contact area. The planar second outside terminal is configured to interface with the support by means of a second contact area. The second contact area has a size in a range between 80% and 120% of a size of the first contact area.

Abstract: A device includes a leadframe having a diepad and leads, a compound semiconductor chip arranged over a first surface of the diepad and including gate, source electrode and drain electrodes, and an encapsulation material covering the compound semiconductor chip and diepad. A second surface of the diepad opposite the first surface is exposed from the encapsulation material. The device also includes a first lead of the leadframe electrically coupled to the gate electrode, a second lead of the leadframe electrically coupled to the source electrode, a third lead of the leadframe electrically coupled to the source electrode, and a fourth lead of the leadframe electrically coupled to the drain electrode. The third lead is configured to provide a sensing signal representing an electrical potential of the source electrode to a gate driver circuit. The gate driver circuit is configured to drive the gate electrode based on the sensing signal.

Abstract: A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

Abstract: A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.

Abstract: A method of manufacturing a hybrid leadframe is provided comprising providing a thin leadframe layer comprising a diepad and a structured region and attaching a metal layer on the diepad, wherein the metal layer has a thickness which is larger than a thickness of the thin leadframe layer.

Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.

Abstract: A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.

Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.

Abstract: A power semiconductor device is provided. The power semiconductor device includes a leadframe, which includes a first chip carrier part and at least one second chip carrier part, which are fitted at a distance from one another and are in each case electrically conductive, at least one first power semiconductor component applied on the first chip carrier part, at least one second power semiconductor component applied on the second chip carrier part, external contacts in the form of external leads, and a capacitor. The capacitor is mounted on two adjacent external leads.

Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.

Abstract: In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant.

Abstract: A device includes a compound semiconductor chip having a control electrode, a first load electrode and a second load electrode. A first lead is electrically coupled to the control electrode, a second lead is electrically coupled to the first load electrode, and a third lead is electrically coupled to the first load electrode. The third lead is configured to provide a sensing signal from the first load electrode, the sensing signal being based on a physical parameter of the compound semiconductor chip. The control electrode is configured to receive a control signal based on the sensing signal. A fourth lead is electrically coupled to the second load electrode.

Abstract: A method of manufacturing a semiconductor power package includes: providing a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing; bonding a power semiconductor chip on the electrically conducting chip carrier; and applying a covering material so as to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.

Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.

Abstract: A semiconductor chip package includes a semiconductor chip disposed over a main surface of a carrier. An encapsulation body encapsulates the chip. First electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a first side face of the encapsulation body. Second electrical contact elements are electrically coupled to the chip and protrude out of the encapsulation body through a second side face of the encapsulation body opposite the first side face. A first group of the first electrical contact elements and a second group of the first electrical contact elements are spaced apart by a distance D that is greater than a distance P between adjacent first electrical contact elements of the first group and between adjacent first electrical contact elements of the second group. The distances D and P are measured between center axes of electrical contact elements.

Abstract: In an embodiment, an electronic component includes a compound semiconductor transistor device having a first current electrode, a second current electrode and a control electrode, a die pad, a first lead, a second lead and a third lead. The first lead, the second lead and the third lead are spaced at a distance from the die pad. The control electrode is coupled to the first lead, the first current electrode is coupled to the die pad and the second current electrode is coupled to the second lead. The third lead is coupled to the compound semiconductor transistor device and provides a source sensing functionality.