Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: A semiconductor device includes a substrate having at least one electrically insulating portion. A first graphene electrode is formed on a surface of the substrate such that the electrically insulating portion is interposed between a bulk portion of the substrate and the first graphene electrode. A second graphene electrode formed on the surface of the substrate. The electrically insulating portion of the substrate is interposed between the bulk portion of the substrate and the second graphene electrode. The second graphene electrode is disposed opposite the first graphene electrode to define an exposed substrate area therebetween.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A microcavity-controlled two-dimensional carbon lattice structure device selectively modifies to reflect or to transmit, or emits, or absorbs, electromagnetic radiation depending on the wavelength of the electromagnetic radiation. The microcavity-controlled two-dimensional carbon lattice structure device employs a graphene layer or at least one carbon nanotube located within an optical center of a microcavity defined by a pair of partial mirrors that partially reflect electromagnetic radiation. The spacing between the mirror determines the efficiency of elastic and inelastic scattering of electromagnetic radiation inside the microcavity, and hence, determines a resonance wavelength of electronic radiation that is coupled to the microcavity. The resonance wavelength is tunable by selecting the dimensional and material parameters of the microcavity. The process for manufacturing this device is compatible with standard complementary metal oxide semiconductor (CMOS) manufacturing processes.

Abstract: A microcavity-controlled two-dimensional carbon lattice structure device selectively modifies to reflect or to transmit, or emits, or absorbs, electromagnetic radiation depending on the wavelength of the electromagnetic radiation. The microcavity-controlled two-dimensional carbon lattice structure device employs a graphene layer or at least one carbon nanotube located within an optical center of a microcavity defined by a pair of partial mirrors that partially reflect electromagnetic radiation. The spacing between the mirror determines the efficiency of elastic and inelastic scattering of electromagnetic radiation inside the microcavity, and hence, determines a resonance wavelength of electronic radiation that is coupled to the microcavity. The resonance wavelength is tunable by selecting the dimensional and material parameters of the microcavity. The process for manufacturing this device is compatible with standard complementary metal oxide semiconductor (CMOS) manufacturing processes.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A method for separating metallic carbon nanotubes and semi-conducting carbon nanotubes includes providing a suspension containing a plurality of individual metallic carbon nanotubes and semi-conducting carbon nanotubes in a liquid, for which the dielectric constant ?L meets the requirement: ?M>?L>?H, wherein ?M is the dieletric constant of the metallic carbon nanotubes and ?H is the dielectric constant of the semi-conducting carbon nanotubes. A a non-homogeneous electric alternating field is applied to the suspension to create spatially separate species of the metallic carbon nanotubes and the semi-conducting carbon nanotubes. At least one of the separate species is then removed.

Abstract: A method for separating metallic carbon nanotubes and semi-conducting carbon nanotubes includes providing a suspension containing a plurality of individual metallic carbon nanotubes and semi-conducting carbon nanotubes in a liquid, for which the dielectric constant ?L meets the requirement: ?M>?L>?H, wherein ?M is the dieletric constant of the metallic carbon nanotubes and ?H is the dielectric constant of the semi-conducting carbon nanotubes. A a non-homogeneous electric alternating field is applied to the suspension to create spatially separate species of the metallic carbon nanotubes and the semi-conducting carbon nanotubes. At least one of the separate species is then removed.

Abstract: A method for separating metallic carbon nanotubes and semi-conducting carbon nanotubes includes providing a suspension containing a plurality of individual metallic carbon nanotubes and semi-conducting carbon nanotubes in a liquid, for which the dielectric constant ?L meets the requirement: ?M>?L>?H, wherein ?M is the dieletric constant of the metallic carbon nanotubes and ?H is the dielectric constant of the semi-conducting carbon nanotubes. A a non-homogeneous electric alternating field is applied to the suspension to create spatially separate species of the metallic carbon nanotubes and the semi-conducting carbon nanotubes. At least one of the separate species is then removed.