Abstract: An adder for use in summing two binary numbers in an arithmetic logic unit of a processor or the like is disclosed and claimed. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.

Abstract: An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.

Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract: An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

Abstract: A dynamic logic gate receives a bias voltage at a data input terminal thereof that is designed to reduce leakage current within the gate. This reduction in leakage current improves the robustness of the dynamic logic gate without requiring the use of performance reducing high threshold voltage transistors within the gate. In one embodiment, the bias voltage is generated using a bootstrap capacitor that is connected to a virtual ground node of a static inverter in a domino logic chain. The bootstrap capacitor causes a small negative voltage to be applied to the virtual ground node in response to a clock signal. Under certain data conditions, the small negative voltage will be coupled to the input terminal of a subsequent dynamic logic gate in the logic chain to reduce leakage current within the subsequent gate.

Abstract: The invention involves a die having domino circuits. In some embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and at least one intermediate node. The domino stage has improved noise immunity and reduced leakage through reverse body biasing transistors in the evaluate network by raising voltage of the at least one intermediate node without static power consumption through the evaluate network. In other embodiments, at least some of the domino circuits include an output stage and a domino stage including a domino stage output node coupled to the output stage. The domino stage includes a wide-fanin evaluate network including the domino stage output node and wherein the domino stage further includes a diode transistor having a gate and an additional terminal connected to the domino stage output node.

Abstract: A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.

Abstract: A signal driver circuit uses a single power supply to provide differential low voltage swing signals for use in an integrated circuit. The driver reduces interconnect voltage swing and power consumption, while improving the speed performance of the interconnect. The driver includes series coupled drive transistors to provide differential signals on integrated circuit interconnects. The driver circuit can include circuitry to place the interconnects in a tri-state condition to allow for shared interconnects. An integrated circuit, such as a processor, includes first and second differential interconnects, a receiver circuit connected to the first and second differential interconnects for detecting a differential voltage provided thereon, and a driver circuit connected to the first and second differential interconnects for providing the differential voltage.

Abstract: In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node. In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes. In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.