Patents by Inventor Ram S. Viswanath

Ram S. Viswanath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104490
    Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Publication number: 20200258759
    Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.
    Type: Application
    Filed: September 29, 2017
    Publication date: August 13, 2020
    Inventors: Wilfred GOMES, Ravindranath V. MAHAJAN, Ram S. VISWANATH
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200066641
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Kemal AYGUN, Richard J. DISCHLER, Jeff C. MORRISS, Zhiguo QIAN, Wilfred GOMES, Yu Amos ZHANG, Ram S. VISWANATH, Rajasekaran SWAMINATHAN, Sriram SRINIVASAN, Yidnekachew S. MEKONNEN, Sanka GANESAN, Eduard ROYTMAN, Mathew J. MANUSHAROW
  • Patent number: 10424561
    Abstract: An integrated circuit (IC) structure includes a first IC package (ICP), including a first resist surface provided with a first plurality of conductive contacts (CCs), a first recess including a second resist surface disposed at a bottom of the recess and having a second plurality of CCs, and a second recess, including a third resist surface disposed at a bottom of the recess and provided with a fourth plurality of CCs. The IC structure further includes an IC component with a first surface and a second surface, the second surface having a third plurality of CCs coupled to the second plurality of CCs of the first ICP. The IC structure further includes a second ICP having a first surface and a second surface, with one or more CCs located at the second surface and coupled to at least one of the first plurality of CCs of the first ICP.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Patent number: 10187996
    Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ram S. Viswanath
  • Publication number: 20180270957
    Abstract: Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package attachable to the PCB, in accordance with some embodiments. In one embodiment, a PCB may include a recess disposed in at least a portion of the PCB, to receive at least a portion of a package. The package may be attachable to the PCB via a plurality of connectors. The connectors may be disposed on a side of the package that faces the PCB. The portion of the package may include one or more discrete components disposed on the side of the package that faces the PCB. The recess may have a depth to accommodate those discrete components that have a height that is greater than a height of the connectors. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 15, 2017
    Publication date: September 20, 2018
    Inventors: Rajasekaran Swaminathan, Ram S. Viswanath
  • Publication number: 20180226381
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: January 5, 2018
    Publication date: August 9, 2018
    Inventors: KYU-OH LEE, ISLAM A. SALAMA, RAM S. VISWANATH, ROBERT L. SANKMAN, BABAK SABI, SRI CHAITRA JYOTSNA CHAVALI
  • Patent number: 9865568
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Islam A. Salama, Ram S. Viswanath, Robert L. Sankman, Babak Sabi, Sri Chaitra Jyotsna Chavali
  • Publication number: 20180007791
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 4, 2018
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Publication number: 20170207196
    Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface.
    Type: Application
    Filed: June 25, 2015
    Publication date: July 20, 2017
    Inventors: KYU-OH LEE, ISLAM A. SALAMA, RAM S. VISWANATH, ROBERT L. SANKMAN, BABAK SABI, SRI CHAITRA JYOTSNA CHAVALI
  • Patent number: 9640887
    Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Ram S. Viswanath
  • Patent number: 9461014
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Publication number: 20160240949
    Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 18, 2016
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, Ram S. Viswanath
  • Patent number: 9391013
    Abstract: 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ram S. Viswanath, Sriram Srinivasan, Mark T. Bohr, Andrew W. Yeoh, Sairam Agraharam
  • Publication number: 20160183374
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9324678
    Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Ram S. Viswanath
  • Patent number: 9265170
    Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ram S. Viswanath, Sanka Ganesan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley, Vijaykumar Krithivasan, David J. Llapitan, Neal E. Ulen, Donald T. Tran