Abstract: Various microscopy probes and methods of fabricating the same are provided. In one aspect, a method of fabricating a microscopy probe is provided that includes providing a member and forming a first film on the member. The first film fosters growth of carbon nanotubes when exposed to a carbon-containing compound. A second film is formed on the first film. The second film has an opening therein that exposes a portion of the first film. A carbon nanotube is formed on the exposed portion of the first film.

Abstract: A semiconductor structure that includes an electrically conductive probe that extends from the back side of an integrated circuit to a selected region within the substrate. The structure includes a substrate having first and second surfaces. An active region is disposed in the substrate, and an electrically conductive probe extends from the first surface of the substrate to the active region. Probes can also be constructed to connect one to another and with well regions within the substrate.

Abstract: An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that enhances the ability to detect photoemissions from the die. According to an example embodiment of the present invention, one of two or more lenses having a higher relative photon count is identified and used to analyze a semiconductor die. The die has at least a portion of the insulator of the SOI structure exposed, and photon emissions are detected using each lens via the exposed insulator in response to the die being stimulated. The number of photons detected using each lens is compared, and the lens having a higher photon count rate is identified, optimizing the photon count for the particular type of die preparation used to expose the insulator. The identified lens is then used with the high-speed detector to detect photoemissions from the die, and the detected photoemissions are used to analyze the die.

Abstract: Methods and apparatus for inspecting a sample are provided. In one aspect, a method of inspection is provided that includes generating an entangled set of particle beams and directing one of the entangled set of particle beams to a location of a workpiece. One of the entangled set of particle beams interacts with the location of the workpiece. One of the entangled set of particle beams is observed after the interaction with the location of the workpiece to inspect the location of the workpiece.

Abstract: According to one aspect of the disclosure, laser-thermal annealing is used to clear an imaging path through the back side of a semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For many applications, thinning results in the formation of crystal defects that inhibit the ability to obtain images through the back side of the semiconductor device. One example embodiment overcomes this problem by thinning via laser-chemical etching the back side of the semiconductor device under a pressure exceeding a threshold level, and then reducing the pressure to a level below the threshold level and scanning the back side of the semiconductor device using a laser at a reduced power level. IR microscopy is then used to capture an image of a circuit in the circuit side of the semiconductor device through the back side of the semiconductor device. One particular example application is directed to a flip-chip semiconductor device.

Abstract: According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

Abstract: An apparatus, system, and method are provided for testing an integrated circuit with a probe card having optical fibers. The optical fibers of the probe card are fixed in alignment with test structures in the integrated circuit, and each optical fiber is coupled to an avalanche photo-diode for measuring photoemissions from the test structures. The photoemissions can be analyzed to verify correct circuit behavior. The optical fibers can be alternatives or complements to electrically conductive probes of the probe card.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the hack side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement from the die that is used for analysis.

Abstract: An integrated circuit die coupled to a package substrate and having circuitry in a circuit side opposite a back side is etched in a manner that inhibits the erosion of underfill material that is used around the periphery of the die and between the die and the package substrate. According to an example embodiment of the present invention, a protective coating adapted to resist etch chemicals is formed over the underfill material. The die is then etched using an etch chemistry that, absent the protective coating, would erode the underfill material. In this manner, etch chemistries that would harm the die, or even be unusable can be used to etch the die. In addition, problems associated with the underfill being eroded, such as die chipping, can be avoided.

Abstract: Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by operating a die and detecting a response that is used to analyze selected characteristics of the die. According to an example embodiment of the present invention, a die having a thinned backside is provided for analysis. The die is operated so that one or more portions of circuitry in the die are near a state-changing transition between a failed mode and a recovered mode. An electron-beam probe is directed to the thinned backside, and the probe electrically couples a capacitance load to underlying circuitry via the insulator of the SOI structure. The capacitance load alters the timing margin of a portion of the circuitry and, thereby, causes the circuitry to undergo a state-changing transition. A response from the circuitry related to the transition is detected and used to analyze the die. In this manner, portions of the die being affected by altered timing margins can be detected.

Abstract: A method and system providing single point high spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A photo-diode optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

Abstract: The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Abstract: A method for detecting substrate damage in a flip chip die, having a back side and a circuit side, that uses magnetic resonance imaging. The back side of the die is first globally thinned down and a region for examination is selected. A magnetic field is applied to the selected region and then the region is scanned with a magnetic resonance imaging arrangement. A plurality of perturbations are measured to generate an array of perturbation signals, which are then converted to a local susceptibility map of the selected region of the die. The susceptibility map of the selected region is then examined to determine if there is any substrate damage.

Abstract: According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of the bulk silicon layer on the back side is removed and a void created. A circuit is formed in the void and is coupled to the existing circuitry on the circuit side of the die. The new circuit is used to analyze the die during operation, testing, or other conditions. The newly formed circuit enhances the ability to analyze the semiconductor die by adding flexibility to the traditional analysis methods used for integrated circuit dice. The newly formed circuit enables many new ways of interactively using the existing circuitry some of which include replacement of defective circuitry, modification of existing circuit operations, and stimulation of existing circuitry for testing.

Abstract: A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

Abstract: According to an example embodiment, a method for testing a semiconductor die is provided. The semiconductor die has circuitry on one side and silicon on an opposite side, and the opposite side may be AR coated. The opposite side is thinned, the die is powered, and a portion of the circuitry is heated to cause a reaction (e.g., a circuit failure or recovery) in a target region. The circuitry is monitored, and the circuit that reacts to the heat is detected and analyzed.

Abstract: Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.

Abstract: The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Abstract: A system and method for analyzing an integrated circuit device involves generating a magnetic field in circuitry forming a power grid within the integrated circuit device. The magnetic field generator is switched off, and the charge on the power grid dissipates through internal device structures to ground. This decay of the charged power grid is detected and evaluated to assess the quality or consistency of the power distribution grid. Faulty power grids will have a decay pattern that differs from high quality power grids.

Abstract: According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.